dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 572

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

NEG.L
Operation:
0 – D→ D
Description: Compute the two’s-complement of a long-word value in memory. When an operand located in mem-
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
A-228
Before Execution
Addresses
(no parallel move)
Word
ory is operated on, the low-order 32 bits of the result are stored back to memory. The condition codes
are calculated based on the 32-bit result. Absolute addresses pointing to long elements must always be
even aligned (that is, pointing to the lowest 16 bits).
This instruction is typically used when integer data is processed.
NEG.L
Prior to execution, the 32-bit value at location $2001:2000 is $00AA:FF00. Execution of the
NEG.L instruction computes the two’s-complement of this value and generates $FF55:0100. The CCR
is updated based on the result of the subtraction.
E
U
N
Z
V
C
LF
15
— Set if the extension portion of the 36-bit result is in use
— Set if the 36-bit result is unnormalized
— Set if bit 31 of the result is set
— Set if the result is zero
— Set if overflow has occurred in result
— Set if a borrow occurs from bit 31 of the result
$2003
$2002
$2001
$2000
P4
14
SR
SR
X:$2000
13
P3
15
X Memory
P2
12
MR
00AA
FF00
030F
030F
0000
0001
DSP56800E Core Reference Manual
P1
11
P0
10
0
Negate Long
; negate the long word at address $2001:2000
I1
9
Assembler Syntax:
NEG.L
I0
8
SZ
7
After Execution
6
L
Addresses
Word
5
E
D
U
4
CCR
$2003
$2002
$2001
$2000
N
3
SR
(no parallel move)
2
Z
15
Freescale Semiconductor
X Memory
V
1
FF55
0319
0000
0001
0100
C
0
NEG.L
0