dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 306

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Pipeline
In the example in Figure 10-13 on page 10-25, the “remaining execution time” is 1 cycle. If n6 is a 2-cycle
instruction with its first decode cycle in cycle #9, the remaining execution time is 2 cycles. If a 2-word,
2-cycle instruction is contained in n5 and n6, the remaining execution time is 1 because there is only 1
remaining instruction cycle once the Int Req takes place.
The preceding timing calculation also applies when pending interrupts are already waiting and interrupts
are enabled by instruction n1.
10.4
The pipeline is normally transparent to the user. However, there are certain instruction sequences that can
cause the pipeline to stall, affecting program execution. Most of these pipeline dependencies and resulting
interlocks occur because the result of an operation occurring very deep in the pipeline is used by the
immediately following instructions that are in earlier stages in the pipeline. Dependencies and interlocks
can also occur when there is contention for an internal resource, such as the status register (SR).
There are three methods for handling pipeline dependencies:
In the first case, dependencies are detected in hardware, and the pipeline automatically stalls for the
required number of cycles. In the second case, the DSC does not stall the pipeline; rather, the assembler
issues a warning and inserts the appropriate number of NOP instructions between the dependent
instructions. In the third case, the assembler generates an error, and the sequence must be re-coded.
10.4.1
There are some cases within the data ALU unit where the nature of the pipeline can result in interlocks and
stalls, affecting the execution of a sequence of instructions. Data ALU dependencies fall into three
different categories:
In most cases, the pipeline will automatically stall when one of these dependencies occurs. In some
instances, NOP instructions are automatically inserted between instructions by the assembler to correct the
dependency.
One common dependency occurs when results that are calculated in the Execute 2 stage of the pipeline are
used as input operands in an immediately following two-stage instruction. Example 10-3 and Table 10-4
on page 10-27 illustrate this type of dependency.
10-26
1. Hardware interlocking—the DSC automatically stalls the pipeline 1 or more cycles
2. Handling by development tools—the assembler automatically inserts NOP instructions
3. Instruction sequence restrictions—the instruction sequence is not allowed
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Interlocks due to two-stage data ALU execution
Dependencies with OMR bits taking effect
Dependencies on reading status bits in the SR
Pipeline Dependencies and Interlocks
Data ALU Pipeline Dependencies
DSP56800E Core Reference Manual
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