dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 440

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

CMP
Operation:
D – S
D – S
Description: Subtract the first operand from the second operand and update the CCR without storing the result. If
Usage:
Note:
Example:
Explanation of Example:
Condition Codes Affected:
A-96
Before Execution
A2
0
(one parallel move)
(no parallel move)
the second operand is a 36-bit accumulator, 16-bit source registers are first sign extended internally
and concatenated with 16 zero bits to form a 36-bit operand. When the second operand is X0, Y0, or
Y1, 16-bit subtraction is performed. In this case, if the first operand is one of the four accumulators;
the FF1 portion (properly sign extended) is used in the 16-bit subtraction (the FF2 and FF0 portions
are ignored).
This instruction can be used for both integer and fractional two’s-complement data.
In order for the carry bit (C) to be set correctly as a result of the subtraction, the operands must be prop-
erly sign extended. The destination can be improperly sign extended by writing the FF1 portion explic-
itly prior to executing the compare, so that FF2 might not represent the correct sign extension. This
note particularly applies to the case in which the source is extended to compare 16-bit operands, such
as X0 with A1.
CMP
Prior to execution, the 36-bit A accumulator contains the value $0:0020:0000, and the 16-bit Y0 reg-
ister contains the value $0024. Execution of the CMP Y0,A instruction automatically appends the
16-bit value in the Y0 register with 16 LS zeros, sign extends the resulting 32-bit long word to 36 bits,
subtracts the result from the 36-bit A accumulator, and updates the CCR (leaving the A accumulator
unchanged).
SZ — Set according to the standard definition of the SZ bit (parallel move)
L
E
U
N
Z
V
C
LF
15
— Set if limiting (parallel move) or overflow has occurred in result
— Set if the extension portion of the result is in use
— Set if result is not normalized
— Set if bit 35 of the result is set
— Set if result equals zero
— Set if overflow has occurred in result
— Set if a carry (or borrow) occurs from bit 35 of the result
0020
2000
P4
14
A1
Y1
Y0,A
13
P3
SR
P2
12
MR
DSP56800E Core Reference Manual
X0,X:(R1)+N
P1
11
0000
0024
0300
A0
Y0
P0
10
I1
9
Compare
Assembler Syntax:
CMP
CMP
I0
8
SZ
; compare Y0 and A, save X0, update R1
7
After Execution
6
L
A2
0
5
E
S,D
S,D
U
4
CCR
0020
2000
A1
Y1
N
3
(one parallel move)
(no parallel move)
SR
2
Z
Freescale Semiconductor
V
1
0000
0024
0319
C
0
A0
Y0
CMP