dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 489
dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
- Current page: 489 of 706
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IMPY.L
Operation:
S1 × S2 → D
Description: Multiply the two signed 16-bit source operands, and place the 32-bit product in the destination (D).
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
Before Execution
A2
B2
0
0
Both source operands must be located in the FF1 portion of an accumulator or in X0, Y0, or Y1. The
destination for this instruction can be an accumulator or the Y register. If an accumulator is used for
the destination, the result is sign extended from bit 31 into the extension portion (FF2) of the accumu-
lator. The result is not affected by the state of the saturation bit (SA).
IMPY.L A1,B1,Y
Prior to execution, the A accumulator contains the value $0:0002:FFFF, the B accumulator contains
$0:FFFE:1234, and the 32-bit Y register contains $0001:37A2. Execution of the IMPY.L instruction
multiplies the 16-bit (signed) positive value in A1 by the (signed) negative 16-bit value in B1, and
stores the (signed) 32-bit negative result ($FFFF:FFFC) into Y. The negative bit is set to indicate the
sign of the result.
L
E
U
N
Z
V
Condition codes are calculated based on the 36-bit result if the destination is an accumulator, and on
the 32-bit result if the destination is the Y register.
LF
15
— Set if overflow has occurred in result
— Set if the extension portion of the result is in use
— Set if the result is unnormalized
— Set if bit 35 (or 31) of the result is set
— Set if the result is zero
— Set if overflow has occurred in result
(no parallel move)
FFFE
0002
0001
P4
14
A1
B1
Y1
13
P3
SR
P2
12
MR
P1
11
Integer Multiply Long
FFFF
37A2
1234
0300
A0
B0
Y0
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
IMPY.L
I0
8
; integer mult with 32-bit result
SZ
7
After Execution
6
L
B2
A2
0
0
5
E
S1,S2,D
U
4
CCR
FFFE
FFFF
0002
B1
Y1
A1
N
3
2
Z
SR
V
(no parallel move)
1
C
0
FFFC
FFFF
1234
0318
IMPY.L
B0
Y0
A0
A-145
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