dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 200

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Address Generation Unit
6.3
The DSP56800E AGU provides several address registers that can be used as pointers for accessing
memory. Not all of the registers work identically, however. Depending on the register, there are additional
capabilities or restrictions of use. For example, the R3 register is the only register that is available for the
secondary read in instructions that perform two data memory moves. Table 6-1 summarizes the
capabilities of each address register.
The type of address arithmetic to be performed, linear or modulo, is not encoded in the instruction, but is
specified by the address modifier register (M01). See Section 6.8, “Linear and Modulo Address
Arithmetic,” for a discussion of the arithmetic types. Table 6-1 indicates whether or not modulo arithmetic
is supported for a given register.
6-6
Register
Pointer
R0
R1
R2
R3
Using Address Registers
(Rn)
(Rn)+
(Rn)–
(Rn)+N
(Rn+N)
(RRR+x)
(Rn+xxxx)
(Rn+xxxxxx)
(Rn)+
(Rn)–
(Rn)+N
(Rn+N)
(RRR+x)
(Rn+xxxx)
(Rn+xxxxxx)
(Rn)+
(Rn)–
(Rn)+N
(Rn+N)
(RRR+x)
(Rn+xxxx)
(Rn+xxxxxx)
(Rn)+
(Rn)–
(Rn)+N
(R3)+N3
(Rn+N)
(RRR+x)
(Rn+xxxx)
(Rn+xxxxxx)
(Rn)
(Rn)
(Rn)
Addressing
Allowed
Modes
Table 6-1. Capabilities of the Address Pointer Registers
Allowed?
Modulo
Yes
Yes
No
No
DSP56800E Core Reference Manual
Counter for the NORM instruction.
Pointer for single parallel move and for primary access in dual parallel reads.
Pointer for P: memory moves.
Optional source register for Tcc transfer.
Supports legacy addressing modes (Rj+N) and (Rj+xxxx).
Shadowed for use with fast interrupt processing.
Refer to Section 6.8.4, “Base Pointer and Offset Values in Modulo Instruc-
tions,” on page 6-26 for interpretation of base pointer and offset in update by
index addressing mode.
Pointer for single parallel move and for primary access in dual parallel reads.
Pointer for P: memory moves.
Optional destination register for Tcc transfer.
Supports legacy addressing modes (Rj+N) and (Rj+xxxx).
Shadowed for use with fast interrupt processing.
Refer to Section 6.8.4, “Base Pointer and Offset Values in Modulo Instruc-
tions,” on page 6-26 for interpretation of base pointer and offset in update by
index addressing mode.
Pointer for single parallel move.
Pointer for P: memory moves.
Supports legacy addressing modes (Rj+N) and (Rj+xxxx).
Pointer for single parallel move and for secondary access in dual parallel
reads.
May be post-updated with N3 register.
Pointer for P: memory moves.
Supports legacy addressing modes (Rj+N) and (Rj+xxxx).
Capabilities and Notes
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