dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 403

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

BFCHG
Operation:
(<bitfield> of destination) → (<bitfield> of destination)BFCHG
Description: Test all selected bits of the destination operand. If all selected bits are set, C is set; otherwise, C is
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Freescale Semiconductor
cleared. Then complement the selected bits, and store the result in the destination. A 16-bit immediate
value is used to specify which bits are tested and changed. Those bits that are set in the immediate value
are the same bits that are tested and changed in the destination; those bits that are cleared in the imme-
diate value are ignored in the destination. This instruction performs a read-modify-write operation on
the destination memory location or register and requires two destination accesses.
This instruction is very useful in performing I/O and flag bit manipulation.
BFCHG
Prior to execution, the 16-bit X memory location X:$5000 contains the value $0010. Execution of the
BFCHG instruction tests the state of bits 4, 8, and 9 in X:$5000, does not set C (because all of the se-
lected bits were not set), and then complements the bits.
For destination operand SR:
For other destination operands:
L
C
If all bits in the mask are cleared, the instruction executes two NOPs and sets the C bit.
Before Execution
X:$5000
LF
15
— Set if data limiting occurred during 36-bit source move
— Set if all bits specified by the mask are set
SR
P4
14
For this destination only, the C bit is not updated as is done for all other destination operands.
All SR bits except bits 14–10 are updated with values from the bitfield unit.
Bits 14–10 of the mask operand must be cleared.
Cleared if at least 1 bit specified by the mask is not set
#$0310,X:$5000
13
P3
P2
12
0010
0301
MR
Test Bitfield and Change
P1
11
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
BFCHG
I0
8
; test and change bits 4, 8, and 9
; in a data memory location
SZ
7
6
L
5
E
After Execution
X:$5000
#iiii,X:<ea> (no parallel move)
#iiii,D (no parallel move)
U
4
CCR
SR
N
3
2
Z
0300
0300
V
1
C
0
BFCHG
A-59