dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 47

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Each of the address registers, R0–R5 and N, can contain either data or an address. All of these registers can
provide an address for the XAB1 and PAB address buses; addresses on the XAB2 bus are provided by the
R3 register. The N offset register can be used either as a general-purpose address register or as an offset or
update value for the addressing modes that support those values. The second 16-bit offset register, N3, is
used only for offset or update values. The modifier register, M01, selects between linear and modulo
address arithmetic.
See Chapter 6, “Address Generation Unit,” for a complete discussion of the AGU.
2.4.6
The program controller is responsible for instruction fetching and decoding, interrupt processing, hardware
interlocking, and hardware looping. Actual instruction execution takes place in the other core units, such as
in the data ALU, AGU, or bit-manipulation unit.
The program controller contains the following:
The operating mode register (OMR) is a programmable register that controls the operation of the
DSP56800E core, including the memory-map configuration. The initial operating mode is typically latched
on reset from an external source; it can subsequently be altered under program control.
The loop address register (LA) and loop count register (LC) work in conjunction with the hardware stack
to support no-overhead hardware looping. The hardware stack is an internal last-in-first-out (LIFO) buffer
that consists of two 24-bit words and that stores the address of the first instruction of a hardware DO loop.
When the execution of the DO instruction begins a new hardware loop, the address of the first instruction
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A 24-bit dedicated stack pointer register (SP)
Two offset registers (N and N3)
A 16-bit modifier register (M01)
A 24-bit adder unit
A 24-bit modulo arithmetic unit
An instruction latch and decoder
The hardware looping control unit
Interrupt control logic
A program counter (PC)
Two special registers for fast interrupts:
— Fast interrupt return address register (FIRA)
— Fast interrupt status register (FISR)
Seven user-accessible status and control registers:
— Two-level-deep hardware stack
— Loop address register (LA)
— Loop address register 2 (LA2)
— Loop count register (LC)
— Loop count register 2 (LC2)
— Status register (SR)
— Operating mode register (OMR)
Program Controller and Hardware Looping Unit
Core Architecture Overview
System Architecture and Peripheral Interface
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