dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 471

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

DO
Explanation of Example:(continued)
Example 2:
Explanation of Example:
Note:
Note:
Freescale Semiconductor
One hardware stack location is used for each nested DO or DOSLC loop. Thus, a two-deep hardware
stack allows for a maximum of two nested loops. The REP instruction does not use the hardware stack,
so repeat loops can be nested within DO loops.
END_CPY
A loop count of zero is specified, so the instructions in the body of the loop are skipped, and execution
continues with the instruction immediately following the loop body.
Note that an immediate loop count of zero for the DO instruction is not allowed and will be rejected
by the assembler. A loop count of zero can only be specified by using a register that is loaded with zero
as the argument to the DO instruction, or by placing a zero in the LC register and executing DOSLC.
A DO loop normally terminates when the body of the loop has been executed for the specified number
of times (the end of the loop has been reached, and LC is one). Alternately, a DO loop terminates if the
count specified is zero, which causes the body of the loop to be skipped entirely.
When the inner loop of a nested loop terminates naturally, the LA2 and LC2 registers are copied into
the LA and LC registers, respectively, restoring these two registers with their values for the outer loop.
A loop is determined to be a nested inner loop if the OMR’s NL bit is set. If the NL bit is not set, the
LA and LC registers are not modified when a loop is terminated or skipped.
If it is necessary to terminate a DO loop early, use one of the techniques discussed in Section 8.5.4.1,
“Allowing Current Block to Finish and Then Exiting,” on page 8-20 and Section 8.5.6.2, “Nesting a
DO Loop Within a DO Loop,” on page 8-22.
During the end-of-loop processing, the NL bit is written into the LF, and the NL bit is cleared. The
contents of the second HWS location (HWS1) are written into the first HWS location (HWS0). Instruc-
tion fetches now continue at the address of the instruction that follows the last instruction in the DO
loop.
DO loops can also be nested as shown in Section 8.5.6, “Nested Hardware Looping,” on page 8-22.
When DO loops are nested, the end-of-loop addresses must also be nested and are not allowed to be
equal. The assembler generates an error message when DO loops are improperly nested.
The assembler calculates the end-of-loop address that is to be loaded into LA by subtracting one from
the absolute address specified in the destination operand. This process occurs to accommodate the case
in which the last instruction in the DO loop is a multiple-word instruction. Thus, the end-of-loop ab-
solute address in the source code must represent the address of the instruction after the last instruction
in the loop.
The LF is cleared by a hardware reset.
Any data dependencies due to pipelining also apply to the pair of instructions formed by the last in-
struction in the DO loop and the first instruction of the DO loop.
MOVE.W
.
.
.
DO
MOVE.L
MOVE.L
Start Hardware DO Loop
#0,X0
X0,END_CPY
X:(R0)+,A
A10,X:(R1)+ ;
Instruction Set Details
; Loop count is zero upon entry
; Copy a 32-bit memory location
DO
A-127