dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 228

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Address Generation Unit
Note that this case requires that the offset N must be a positive two’s-complement integer. This technique
is useful in sequentially processing multiple tables (for example, implementing a bank of parallel IIR
filters) or N-dimensional arrays. The primary address arithmetic unit will automatically wrap around the
address pointer by the required amount.
6.8.9
Due to the way modulo arithmetic is implemented by the DSP56800E, there are some potential side effects
that must be noted. Specifically, there are some restrictions and limitations that relate to the fact that the
base address of a buffer must be a power of two, and that the modulo arithmetic unit can only detect a
single wraparound.
6.8.9.1
If a pointer is outside the valid modulo buffer range, and an operation occurs that causes R0 or R1 to be
updated, the contents of the pointer are still updated using modulo arithmetic. This can result in the pointer
register being updated with an unexpected value, resulting in unusual behavior. Care should be taken to
ensure that the R0 and R1 pointers always point into a valid modulo buffer when modulo address
arithmetic is enabled.
For example, a
leave R0 unchanged since N is zero. However, since R0 is outside the boundary, the address calculation is
R0 + N - (M01 + 1) for the new contents of R0 and sets it to 0.
6.8.9.2
The modulo arithmetic unit in the AGU is only capable of detecting a single wraparound of an address
pointer. As a result, if the post-update addressing mode—(Rn)+N—is used, be careful in selecting the
value of N. The 16-bit absolute value |N| must be less than or equal to M01 + 1 for proper modulo
addressing. Values of |N| that are larger than the size of the buffer may result in the Rn address value
wrapping twice, which the AGU cannot detect.
6.8.9.3
When the size of a modulo buffer is not a power of two, there is a range of memory locations immediately
after the buffer that are not accessible with modulo addressing. Lower boundaries for modulo buffers
always begin on an address where the lowest k bits are zeros—that is, a power of two. This requirement
means that for buffers that are not an exact power of two, there are locations above the upper boundary that
are not accessible through modulo addressing.
In Figure 6-8 on page 6-22, for example, the buffer size is 37, which is not a power of two. The smallest
power of two that is greater than 37 is 64. Thus, there are 64 – 37 = 27 memory locations that are not
accessible with modulo addressing. These 27 locations are between the upper boundary + 1 = $00A5 and
the next power-of-two boundary address – 1 = $00C0 – 1 = $00BF.
These locations are still accessible when modulo arithmetic is not performed. Using linear addressing
(with the R2–R5 pointers), absolute addresses, or the no-update addressing mode makes these locations
available.
6-34
Side Effects of Modulo Arithmetic
When a Pointer Lies Outside a Modulo Buffer
Restrictions on the Offset Register
Memory Locations Not Accessible Using Modulo Arithmetic
MOVE.W B,X:(R0)+N
DSP56800E Core Reference Manual
instruction (where R0 = 6, M01 =5, and N = 0) would apparently
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