dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 291

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

10.3.3
Interrupts on the DSP56800E architecture can be nested; one exception can interrupt another exception’s
interrupt service routine if it has a higher priority. During initial interrupt processing, interrupts are
disabled. Once the JSR instruction reaches the point in the pipeline where it has begun execution, the core
can safely re-enable interrupts because the return address will be stacked properly before another interrupt
can occur. This re-enabling occurs at cycle #11 in Figure 10-4 on page 10-12. Interrupts are disabled
during cycles #4 through #10.
If a second, higher-priority interrupt request occurs after cycle #4, it is not arbitrated until after interrupts
are re-enabled in cycle #11. This scenario is illustrated in Figure 10-4 as interrupt request i2a. The second
interrupt request interrupts the processing of the first at cycle #13, and it is processed before the interrupt
handler for request i1 resumes.
If the vector table contains a 2-word JSR instruction, no interrupts are allowed between the JSR and the
first instruction in the interrupt service routine (ii2). If the vector table contains a 3-word JSR instruction,
interrupts are permitted between the JSR instruction and the first instruction in the interrupt service routine
(ii2).
10.3.4
Another case of interest is where a first interrupt request begins the interrupt pipeline and the instruction at
n1 in Figure 10-4 on page 10-12 is a non-maskable SWI instruction or an illegal instruction. The SWI and
illegal instructions execute in 4 clock cycles. Upon completion of these cycles, the exception that is
serviced will not be the original interrupt request. Instead, the core will service the SWI or illegal
instruction exception that is caused by instruction n1. This condition is true only when the first interrupt
request is at a lower priority level than the exception that is caused by the instruction at n1.
Freescale Semiconductor
Nested Interrupts
SWI and Illegal Instructions During Interrupt
Processing
Instruction Pipeline
Pipeline During Interrupt Processing
10-11