dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 491

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

IMPY.W
Operation:
S1 × S2 → D
Description: Perform an integer multiplication on the two 16-bit, signed, integer source operands (S1 and S2), and
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Freescale Semiconductor
Before Execution
A2
4
store the lowest 16 bits of the integer product in the destination (D). If the destination is an accumula-
tor, the product is stored in the MSP with sign extension while the LSP remains unchanged. The order
of the first two operands is not important. The V bit is set if the calculated integer product does not fit
into 16 bits. The result is not affected by the state of the saturation bit (SA).
This instruction is useful in general computing when it is necessary to multiply two integers and the
nature of the computation can guarantee that the result fits in a 16-bit destination. In this case, it is bet-
ter to place the result in the MSP (FF1 portion) of an accumulator because more instructions have ac-
cess to this portion than to the other portions of the accumulator.
IMPY.W A1,Y0,A
Prior to execution, the A accumulator contains the value $4:0002:1234, and the data ALU register Y0
contains the 16-bit (signed) negative integer value $FFFE. Execution of the IMPY.W instruction inte-
ger multiplies the (signed) positive value in A1 and the (signed) negative value in Y0, and stores the
(signed) negative result ($FFFC) in A1. A0 remains unchanged, and A2 is sign extended. The negative
bit is set to indicate the sign of the result.
L
N
Z
V
A 31-bit integer product is calculated for this instruction, while the lowest 16 bits are stored in the des-
tination register. When SA or CM are set, the N bit is set to the value in bit 30 of the internally com-
puted result. When SA and CM are zero, the N bit is set to the value in bit 15 of the result.
LF
15
— Set if overflow has occurred in the 16-bit result
— Set if bit 15 of the result is set
— Set if the 16-bit result or 20 MSBs of a destination accumulator equal zero
— Set if overflow occurs in the 16-bit result
(no parallel move)
0002
2000
P4
14
A1
Y1
13
P3
SR
P2
12
MR
P1
11
Integer Multiply Word
FFFE
0300
1234
A0
Y0
P0
10
Instruction Set Details
; integer 16-bit multiplication
I1
9
Assembler Syntax:
IMPY.W
I0
8
SZ
7
After Execution
6
L
A2
F
5
E
S1,S2,D
U
4
CCR
FFFC
2000
A1
Y1
N
3
SR
2
Z
V
(no parallel move)
1
FFFE
0308
1234
C
IMPY.W
0
A0
Y0
A-147