dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 302

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Pipeline
10.3.8
Interrupt latency is the time between when an interrupt request first appears and when the first instruction
in an interrupt service routine is actually executed. The interrupt can only take place on instruction
boundaries (which are subject to the non-interruptible sequences that are described in Section 9.3.4,
“Non-Interruptible Instruction Sequences,” on page 9-10). The length of execution of an instruction can
affect interrupt latency.
For purposes of calculation, interrupt latency is defined here as the time between when the interrupt
controller first arbitrates among the interrupt sources and when the first instruction in an interrupt handler
is latched into the instruction latch and is ready to be executed. This first instruction is defined as the
instruction that is executed immediately after the JSR from the interrupt vector table. See Figure 10-10.
10.3.8.1
Interrupt latency is calculated as follows:
The largest execution time for instruction n1 is 8 clock cycles (when n1 is an RTI or RTS instruction). See
Section 10.3.8.3, “Cases That Increase Interrupt Latency.”
10-22
Pipeline
Int Arbitr
Int Req
Stage
OP2
EX2
AG
EX
P1
P2
IF
ID
Latency = Execution time of instruction n1
Interrupt Latency
Interrupt Latency
n1 n2 n3 n4 ii0 ii1 ii1
1
n1 n2 n3 n4 ii0 ii1
2
+ 4 clock cycles (1 for arbitration and 3 NOPs)
+ the number of clock cycles to execute the JSR (4 or 5 cycles)
+ wait states when the JSR instruction pushes the PC and SR to the stack
+ wait states due to program fetches of n3, n4, and ii0–ii3
(or ii0–ii4 if the JSR instruction executes in 5 cycles)
n1 n2 n3 n4 ii0
3
i
n1 — — —
4
i
n1 — —
Interrupt Request Sampled
Figure 10-10. Interrupt Latency Calculation
5
n1 —
6
DSP56800E Core Reference Manual
by the Arbiter
n1
7
jsr
n1
ii1
ii1
ii1
—
—
—
8
ii2
ii1
ii1
jsr
jsr
—
—
—
9
10
ii3
ii2
ii1
jsr
jsr
jsr
—
—
Instruction Cycle
11
jsr
jsr
jsr
jsr
ii4
ii3
ii2
—
12
ii4
ii3
ii2
jsr
jsr
jsr
jsr
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First Instruction in Handler Reaches
13
ii4
ii3
ii2
jsr
jsr
jsr
•
•
14
ii4
ii3
ii2
jsr
jsr
•
•
•
Instruction Decode
15 16 17 18 19 20 21 22
jsr
ii4
ii3
ii2
•
•
•
•
ii4
ii3 ii4
ii2 ii3 ii4
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