dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 151

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

As Figure 5-4 on page 5-4 shows, it is also possible to directly address the 32-bit long-word portion of the
accumulator, which is referred to as FF10 in this notation. FF10 represents the concatenation of the FF1
and FF0 portions and is useful for manipulating 32-bit quantities.
The accumulators are used as source or destination operands for most data ALU operations. With the use
of parallel move instructions (see Section 3.3.5, “Parallel Moves,” on page 3-11), these registers can serve
as sources for data ALU operation while new operands are loaded into them, in parallel, from memory.
This process is demonstrated in Example 5-2.
Each register can be read or written as a byte, word, or long operand. In a parallel move instruction, an
accumulator register is specified only as a whole accumulator and not in portions. Only the C register can
be written by the secondary read in a dual read instruction.
Section 5.2, “Accessing the Accumulator Registers,” discusses methods for accessing the accumulators
and strategies for using them properly.
5.1.3
The multiply-accumulator (MAC) and logic unit is the main arithmetic processing unit in the data ALU.
This block performs multiplications, additions, subtractions, logical operations, and other arithmetic
operations. It accepts up to three input operands and outputs one 36-bit result.
The MAC unit is pipelined to maintain a throughput of one instruction per cycle. The MAC pipeline has
two stages, multiplication and arithmetic/logical. Multiplication and MAC operations take 2 cycles to flow
through the two pipeline stages, whereas arithmetic and logical operations are completed in a single cycle.
More information on the two-stage execution of the MAC unit appears in Section 10.2.2, “Data ALU
Execution Stages,” on page 10-4.
The inputs of the MAC and logic unit can come from the seven data ALU registers (A1, B1, C1, D1, X0,
Y0, and Y1), can come from memory, or can be immediate data. Byte, word, and long operands are all
supported. Optional saturation and rounding are supported to ensure correct operation when 36-bit results
are written to memory. See Section 5.9, “Rounding,” for a more detailed discussion.
Arithmetic operations in the MAC unit occur independently and in parallel with memory accesses on the
core data buses. This capability allows a parallel move instruction to update an accumulator in the same
instruction in which the accumulator is used as the source for an ALU operation.
5.1.4
The accumulator shifter is an asynchronous parallel shifter with a 36-bit input and a 36-bit output. The
accumulator shifter is used to perform single-bit shifts of entire accumulators (as with the ASL and ASR
instructions), or to pre-shift values before they are passed on to the MAC unit (as occurs with the LSRAC
instruction).
Freescale Semiconductor
Multiply-Accumulator (MAC) and Logic Unit
Single-Bit Accumulator Shifter
ADD.W
Example 5-2. Accumulator A Used in Operation and Stored in Parallel
The C2, C0, D2, and D0 portions of the C and D accumulators are
generally not directly accessible through the instruction set, with the
exception of certain operations. See Section 5.2.2, “Accessing Portions of
an Accumulator,” for ways to access these registers.
X0,A
A,X:(R0)+
Data Arithmetic Logic Unit
; A used and simultaneously stored
NOTE:
Data ALU Overview and Architecture
5-5