dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 701

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
MOVEU.BP instruction 4-9, 4-21, A-210
MOVEU.W instruction 4-9, 4-23, 4-26 to 4-28, A-213
MPY instruction 4-2, 4-28, 4-48 to 4-49, A-216
MPYR instruction 4-2, 4-29, 4-48 to 4-49, 5-43,
MPYSU instruction 4-2, 4-30, 5-28, A-222
multi-bit shifting instructions 4-5, 4-38
multiplication 5-18
multiplication instructions 4-2
multiply-accumulator (MAC) unit 5-5
N
N, see offset registers (N and N3) and negative bit (N)
N3, see offset registers (N and N3)
NEG instruction 4-3, 4-35, 4-48, A-224
NEG.BP instruction 4-3, 4-35, A-226
NEG.L instruction 4-4, 4-35, A-228
NEG.W instruction 4-4, 4-35, A-230
NEGA instruction 4-7, 4-42, A-232
negative bit (N) 8-9
nested hardware looping 8-11 to 8-12, 8-22 to 8-23
nested interrupts 10-11, 10-14
nested looping bit (NL) 8-7, 8-18
NL, see nested looping bit (NL)
NOP instruction 4-10, 4-47, 8-23, A-233
NORM instruction 4-4, 4-40, 5-37, 10-3, A-234
normal interrupt processing 9-5
normal processing state 9-1, 11-6
normalizing 5-36 to 5-37, 8-9
NOT.W instruction 4-6, 4-40, A-236
NOTC instruction 4-6, 4-11, 4-14 to 4-15, 7-1, A-237
O
odd alignment 3-19, 5-14, 9-9, A-28, A-191
offset registers (N and N3) 2-9, 6-3, 6-5
OMR, see operating mode register (OMR)
on-chip emulation, see Enhanced On-Chip Emulation
operand remapping 4-11, 5-21
operating mode bits (MB and MA) 8-6, 9-2
operating mode register (OMR) 2-9, 5-41, 8-4, 8-12,
extended-precision 4-29
fractional 5-18
integer 5-18 to 5-19
multi-precision 5-29, 5-32, 5-35
signed 5-33 to 5-34
single-precision 5-28
unsigned 5-28, 5-34
using ASLL.L 5-37
using NORM 5-37
addressing modes 4-12
duplicate operands 4-11
A-219
(Enhanced OnCE) module
8-25 to 8-26, 9-12
Index
OR.L instruction 4-6, 4-40, A-238
OR.W instruction 4-6, 4-40, A-240
ORC instruction 4-6, 4-11, 4-14 to 4-15, 7-1, A-241
overflow
overflow bit (V) 8-9
P
P: (memory symbol) 3-9
P4–P0, see program counter extension bits (P4–P0)
PAB, see program memory address bus (PAB)
parallel moves 3-8, 5-4 to 5-5
PC, see program counter (PC)
PDB, see program data bus (PDB)
peripheral registers 3-10
peripherals 9-2
phase-locked loop (PLL) 1-3
pipeline 10-1
PLL, see phase-locked loop (PLL)
popping the stack 8-15
power consumption 9-11 to 9-12
primary data address bus (XAB1) 2-7
processing states 9-1, 11-6
program control instructions 4-9
program controller registers 3-5
program counter (PC) 8-1, 8-3, 8-11
program counter extension bits (P4–P0) 8-11
program data bus (PDB) 2-7
program memory address bus (PAB) 2-7
programming languages, high-level 1-1 to 1-2, 6-11,
programming model (core) 2-2, 3-1
pushing the stack 8-14
condition code mode bit (CM) 8-7
external X memory bit (EX) 8-6
nested looping bit (NL) 8-7
operating mode bits (MB and MA) 8-6
rounding bit (R) 8-6
saturation bit (SA) 8-6
stop delay bit (SD) 8-6
X or P memory bit (XP) 8-6
arithmetic 8-9
division 5-24
dual parallel reads 3-11 to 3-12, 4-49, 6-2
instructions for 3-11
single parallel moves 3-11 to 3-12, 4-48
dependencies 10-26
stalls 4-12, 10-26
debug 9-13
exception 9-2
normal 9-1
reset 9-1
stop 9-12
wait 9-11
8-16
Index-v