dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 356
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dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
- Current page: 356 of 706
- Download datasheet (4Mb)
ADD
Operation:
S + D →
S + D →
S + D →
Description: Add the source register to the destination register and store the result in the destination (D). If the des-
Usage:
Example:
Explanation of Example:
Note:
A-12
Before Execution
A2
X0
D
D
D
0
tination is a 36-bit accumulator, 16-bit source registers are first sign extended internally and concate-
nated with 16 zero bits to form a 36-bit operand (the Y register is only sign extended). When the des-
tination is X0, Y0, or Y1, 16-bit addition is performed. In this case, if the source operand is one of the
four accumulators, the FF1 portion (properly sign extended) is used in the 16-bit addition; the FF2 and
FF0 portions are ignored. Similarly, if the destination is the Y register, the FF2 portion is ignored.
This instruction can be used for both integer and fractional two’s-complement data.
ADD
Prior to execution, the 16-bit X0 register contains the value $0002, and the 36-bit A accumulator con-
tains the value $0:0058:1234. The ADD instruction automatically appends the 16-bit value in the X0
register with 16 LS zeros, sign extends the resulting 32-bit long word to 36 bits, and adds the result to
the 36-bit A accumulator. A new word is read into the X0 register and address register R2 is updated
by –1.
The carry bit (C) in the CCR is set correctly using word or long-word source operands if the extension
register of the destination accumulator contains sign extension from bit 31 of the destination accumu-
lator. C is always set correctly using accumulator source operands.
R2
(no parallel move)
(one parallel move)
(two parallel reads)
N
0058
0002
A1
X0,A
SR
FFFFFF
002001
DSP56800E Core Reference Manual
X:(R2)+N,X0 ; 16-bit addition, load X0, update R2
1234
0300
A0
ADD
Assembler Syntax:
ADD
ADD
Add
After Execution
A2
X0
0
S,D
S,D
S,D
R2
N
005A
3456
A1
(no parallel move)
(one parallel move)
(two parallel reads)
SR
FFFFFF
002000
Freescale Semiconductor
0310
1234
A0
ADD
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