dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 568

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

NEG
Operation:
0 – D →
0 – D →
Description: The destination operand (D) is subtracted from zero, and the two’s-complement result is stored in the
Example:
Explanation of Example:
Note:
Condition Codes Affected:
A-224
Before Execution
B2
D
D
0
destination (D). If the destination is a 16-bit register, it is first sign extended internally and concatenat-
ed with 16 zero bits to form a 36-bit operand (the Y register is only sign extended).
NEG
Prior to execution, the 36-bit B accumulator contains the value $0:00AA:FF00. The NEG instruction
takes the two’s-complement of the value in the B accumulator and stores the 36-bit result
($F:FF55:0100) back in the B accumulator. The value for X0 is stored in memory and the address reg-
ister R3 is post-incremented by one. The N bit is set because the result is negative.
When the D operand equals $8:0000:0000 (–16.0 when interpreted as a decimal fraction), the NEG
instruction causes an overflow to occur since the result cannot be correctly expressed using the stan-
dard 36-bit, fixed-point, two’s-complement data representation. When saturation is enabled (the OMR
register’s SA bit is set to one), data limiting will occur to value $F:8000:0000. If saturation is not en-
abled, the value will remain unchanged.
SZ — Set according to the standard definition of the SZ (parallel move)
L
E
U
N
Z
V
C
LF
15
— Set if limiting (parallel move) or overflow has occurred in result
— Set if the extension portion of result is in use
— Set according to the standard definition of the U bit
— Set if bit MSB of result is set
— Set if the result equals zero
— Set if overflow has occurred in the result
— Set if a borrow is generated from the MSB of the result
(no parallel move)
(one parallel move)
00AA
P4
14
B1
B
13
P3
SR
P2
12
MR
DSP56800E Core Reference Manual
P1
11
X0,X:(R3)+
FF00
0300
B0
P0
10
Negate Register
I1
9
Assembler Syntax:
NEG
NEG
I0
8
; 0 - B → B, save X0, update R3
SZ
7
After Execution
6
L
B2
F
5
E
D
D
U
4
CCR
FF55
B1
N
3
(no parallel move)
(one parallel move)
SR
2
Z
Freescale Semiconductor
V
1
0100
0319
C
0
B0
NEG