dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 658

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

A.3
The following sections describe the notation that is used in the “Instruction Opcode” sections of the
instruction descriptions. This information allows instructions to be manually encoded into a binary pattern
or to be decoded from their binary form.
Figure A-1 shows an example of how instruction encodings are presented. In the grid on the right-hand
side, each box represents a single bit in the opcode. Where the bit is given as a binary digit, it represents the
actual value that is encoded in that position in the opcode. A letter in one of the bit positions indicates that
the encoding is variable, based on the operands or memory accesses that are used in the instruction.
In the example opcode for the MPY instruction in Figure A-1, five variable encoding fields are specified:
GGG, F, QQQ, m, and RR. Consult the tables in the following sections to determine their use, as follows:
Using the values in the tables that follow this section, we can construct the encoding for the instruction
MPY Y1,B1,A
The tables in the following sections give the encoding fields that are used in the instruction encodings.
A-314
MPY
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•
•
•
•
GGG specifies the destination register for the parallel move.
F specifies the destination register for the multiplication.
QQQ designates the two source registers for the multiplication.
m selects the addressing mode that is used by the parallel move.
RR selects the register holding the parallel move source address.
Instruction Opcode Encoding
Q1,Q2,F X:<ea_m>,GGG
Y1 as destination of parallel move
Figure A-2. Encoding for the MPY Y1,B1,A
15
0
X:(R1)+,Y1
A register as destination for MPY
0
1
12
0
Figure A-1. Example Instruction Encoding
11
as shown in Figure A-2.
0
DSP56800E Core Reference Manual
1
15
0
1
0
1
8
1
0
7
Y1 and B1 as source to MPY
12
0
0
11
0
0
G
1
4
(Rn)+ addressing mode
G
1
3
X:(R1)+,Y1 Instruction
G
8
0
R1 register as source for parallel move
F
7
0
Q
1
0
Q
Freescale Semiconductor
Q
4
1
3
m
R
R
0