dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 195

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Chapter 6
Address Generation Unit
The address generation unit (AGU) performs all address calculation and generation for the DSP56800E
core. The AGU calculates effective addresses for instruction operands and directly executes the address
arithmetic instructions.
Support is built into the AGU for applications that require both 24- and 16-bit pointers. Byte, word, and
long-word data memory accesses are also available for use by applications. Extensive pointer arithmetic
operations are provided for even greater flexibility.
6.1
The address generation unit (AGU) consists of the registers and logic used to calculate the effective
address of data operands in memory. It supports both linear and modulo arithmetic calculations. All AGU
operations are performed in parallel with other chip functions to minimize address-generation overhead.
The major components of the address generation unit are:
The AGU contains two arithmetic units—a primary address arithmetic unit for complex address
calculations, and a secondary address adder for simple calculations. The primary address arithmetic unit
supports both linear and modulo address arithmetic, simplifying the implementation of some useful data
structures.
The two arithmetic units can update up to two 24-bit addresses every instruction cycle: one for primary
memory accesses using XAB1 or PAB, and one for secondary memory accesses performed on XAB2.
AGU operations are performed on internal AGU buses, so bus transfers occur in parallel with AGU
calculations.
Figure 6-1 on page 6-2 presents a block diagram of the AGU.
Freescale Semiconductor
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A 24-bit primary address arithmetic unit.
A 24-bit secondary address adder unit.
Two single-bit shifters for byte addressing.
AGU Architecture
Address Generation Unit
6-1