dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 605

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

SAT
Operation:
Saturate S → D
Saturate S → Y0
Description: Transfer the value in an accumulator to another register, substituting a positive or negative fixed con-
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
Before Execution
A2
A2
B2
C
3
3
stant if necessary to prevent the value from overflowing the destination register. The result is not af-
fected by the state of the saturation bit (SA). The algorithm that is used to determine if the constant
should be substituted is discussed in Section 5.8, “Saturation and Data Limiting,” on page 5-39.
This instruction is used to force saturation to take place. If the SA bit in the operating mode register
has been cleared, disabling saturation, the SAT instruction can be used after a calculation to manually
force saturation.
SAT B,Y0 A,X:(R2)+
Prior to execution, R2 contains the value $1000, and the B accumulator contains the value
$3:A000:00FF. Since this value makes use of the extension register (it does not contain just sign ex-
tension), this value cannot be represented by a 16-bit word, and transferring the value to the Y0 register
would result in overflow. When the SAT instruction is executed, it substitutes the largest positive in-
teger, resulting in a value of $7FFF in Y0. The parallel write has a similar effect since the value in A
($C:A000:00FF) cannot be represented by a 16-bit word. This value is saturated to the maximum
16-bit negative value and $8000 is written to memory. The L bit is set because limiting occurs in the
parallel move. The value of R2 is post-incremented by one.
SZ — Set by result of parallel write to memory according to the standard definition
L
LF
15
— Set if overflow has occurred in the parallel move
(no parallel move)
(one parallel move)
A763
A000
A000
2000
P4
14
A1
A1
B1
Y1
This bit is not affected by the SAT operation.
X:$1000
13
P3
SR
P2
12
MR
P1
11
00FF
00FF
4226
0000
F799
0300
A0
A0
B0
Y0
P0
10
Instruction Set Details
; transfer value in B to Y0, with saturation
; store A1 (with limiter active) to memory
; and update pointer
I1
9
Saturate
Assembler Syntax:
SAT
SAT
I0
8
SZ
7
After Execution
6
L
A2
A2
B2
C
3
3
5
E
S,D
S,Y0
U
4
CCR
A763
A000
A000
2000
A1
A1
B1
Y1
X:$1000
N
3
(no parallel move)
(one parallel move)
SR
2
Z
V
1
7FFF
03C0
00FF
00FF
4226
8000
C
0
A0
A0
B0
Y0
SAT
A-261