dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 270

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Processing States
Every interrupt source has an associated priority level. For some interrupt sources, such as the SWI
instructions and non-maskable interrupts, the interrupt level is pre-assigned. Other interrupt sources, such
as on-chip peripherals, support a programmable priority level. Programmable interrupt sources other than
those in the debug port can be set to one of the maskable priority levels (0, 1, or 2) or be disabled.
Enhanced OnCE interrupt sources can be programmed as level 1, 2, or 3 or as disabled. The CCPL is set to
level 3 on reset.
When an exception or interrupt is recognized and the CCPL is low enough to allow it to be processed, the
CCPL is automatically updated to be one higher than the level of the interrupt (except for the case of
SWILP, which does not update the CCPL, or the case of level 3 interrupts, which leave the priority level at
level 3). This updating prevents interrupts that have the same or a lower priority level from interrupting the
handler for the current interrupt. When the interrupt service routine finishes, the CCPL is set back to its
original value.
To better understand the interrupt priority structure, consider a simple example with nested interrupts.
Assume that the following have already taken place:
Now consider that a second peripheral, a timer with interrupt priority level 0, generates an interrupt.
Although the interrupt request is valid, the interrupt will not be acknowledged and serviced because the
peripheral’s priority level is lower than the core’s CCPL. If the interrupt request can be latched as pending,
the interrupt will be serviced after the current interrupt service routine completes, because the CCPL will
be restored to its original level (level 0). A higher-priority interrupt (at level 2, for instance) would
interrupt the level 1 service routine, and the level 1 routine would resume later after the level 2 handler
completed.
9.3.2
When an interrupt or exception occurs, the current program is stopped, and control is passed to an interrupt
handling routine. Once the handling routine has completed processing the interrupt, control is returned to
the original program at the point at which it was interrupted. The location of the interrupt handling routine
that is to be executed is determined with the interrupt vector table.
Interrupt vectors are typically located in a block of memory locations in program memory (although
interrupt vectors can be located anywhere in the program memory map, if desired). Each interrupt vector
typically holds a 2- or 3-word JSR instruction, except for fast interrupts, which are covered in
Section 9.3.2.2, “Fast Interrupt Processing.” When an interrupt occurs, the interrupting device provides a
vector number to the core. Program control is then transferred to the address specified by the vector
provided. At this address, the JSR instruction is fetched and executed, transferring control to the interrupt
service routine. Figure 9-1 on page 9-5 shows an example of the vector table.
When the chip is in data-memory execution mode (see Section 8.6, “Executing Programs from Data
Memory,” on page 8-23), the interrupt vector table is located in data memory, not program memory, and
the interrupt vector is fetched appropriately from data memory when entering exception processing.
9-4
1. A serial port on a chip has requested a level 1 interrupt when the core’s CCPL was at level 0.
2. The core has recognized this interrupt and entered the exception processing state. The
3. Program flow has been transferred to the interrupt handler for the serial port.
CCPL was updated from level 0 to level 2, which is one level higher than the priority of the
recognized interrupt (level 1).
Interrupt and Exception Processing
DSP56800E Core Reference Manual
Freescale Semiconductor