dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 300

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Instruction Pipeline
Figure 10-9 on page 10-21 shows the fast interrupt pipeline for the case of a short fast interrupt service
routine where the following occur:
In this case, the instructions in the FRTID’s are multi-cycle instructions such that the 2 delay slots execute
in 4 cycles.
For the fast interrupt service routine in this example, control does not return to the main program but
instead immediately enters the second interrupt. This is true anytime the instructions in the FRTID’s delay
slots execute in 4 or more cycles.
If the second interrupt is level 0, 1, or 2, successful arbitration occurs in cycle #12 because the FRTID
instruction must first restore the status register. If the second interrupt request is level 3, arbitration begins
1 cycle earlier in cycle #11. The level 3 interrupt completes successful arbitration 1 cycle earlier. The
exception processing state, however, can only be entered upon the completion of an instruction. Since the
second cycle of the FRTID instruction executes after the completion of the instructions in the delay slots,
the exception processing state is entered at the same time, regardless of the priority level of the second
interrupt.
Consider another scenario that is not shown in Figure 10-9: If the instructions in the FRTID’s 2 delay slots
execute in 3 clock cycles, then 1 instruction from the main program, n2, will be executed before the second
interrupt is entered.
10-20
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A fast interrupt request is received.
Simultaneously with this request or a short time after it is received, a second interrupt is received.
DSP56800E Core Reference Manual
Freescale Semiconductor