dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 679

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

(OMR).
The following bits are affected by the MAC output limiter:
The following bits are only affected in unusual cases:
Condition code calculation is not affected by the MAC output limiter for most test and comparison
instructions. However, it is possible for the MAC output limiter to affect the calculation of the U bit when
the CMP.W instruction is executed. See Section B.3, “Condition Code Summary by Instruction,” for more
information.
The MAC output limiter only affects operations in the data ALU. Move instructions, bit-manipulation
B.1.2
The DSP56800E contains a MAC output limiter that can be enabled to perform automatic saturation on the
results of many data ALU operations before they are stored back into an accumulator. When saturated,
results are limited to fit within the FF1:FF0 portion of the accumulator, with the extension portion
containing only sign extension. Because results are limited to 32 bits, condition code calculation can be
affected. The MAC output limiter is enabled through setting the SA bit in the operating mode register
instructions, and AGU instructions are not affected. See Section 5.8.3, “Instructions Not Affected by the
MAC Output Limiter,” on page 5-42 for a complete list of data ALU instructions that are not affected.
B.1.3
The data ALU’s condition code mode also affects condition code calculation. There are two condition code
modes: 36-bit mode, where the extension portion of the accumulator (the FF2 portion) is used when
condition codes are calculated, and 32-bit mode, where the extension registers are ignored. The mode is
selected using the condition code mode bit (CM) in the OMR. When this bit is set, 32-bit mode is selected,
and the accumulator extension registers are ignored when condition codes are calculated. When the CM bit
is cleared, 36-bit condition code mode is used.
Signed values can be computed in either way, but pay attention to the condition code mode when
performing unsigned operations. For correct operation, 32-bit condition code mode (CM bit set) must be
selected when TST and CMP instructions are executed before jump and branch instructions that use the HI,
HS, LO, or LS branch and jump conditions.
The condition code mode directly affects the following condition code bits:
Freescale Semiconductor
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U—Cleared if saturation occurs in the MAC output limiter
V—Set when saturation occurs in the MAC output limiter
L—May be indirectly affected through effects on V bit
N—Affected only when ASRAC, LSRAC, or IMPY.W are executed
C—Affected only by ASL
V—Set based on the MSB of the result’s MSP portion versus the extension portion
Z—Set using only the MSP and LSP portions of the result versus the whole accumulator
MAC Output Limiter
Condition Code Mode
When the MAC output limiter is enabled, condition codes are not always
set in an intuitive manner. It is best to examine each instruction to
determine the effect of the MAC output limiter on condition code
calculation.
Condition Code Calculation
NOTE:
B-3