dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 697

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

accumulator most significant product registers, see most
accumulator registers (A, B, C, and D) 2-8, 3-2 to 3-3,
ADC instruction 4-3, 4-14, 4-30, A-10
ADD instruction 4-3, 4-30, 4-48 to 4-49,
add with carry 4-30
ADD.B instruction 4-3, 4-30, A-16
ADD.BP instruction 4-3, 4-30, A-17
ADD.L instruction 4-3, 4-31, A-19
ADD.W instruction 4-3, 4-14, 4-31, A-21
ADDA instruction 4-7, 4-12, 4-41, A-24
ADDA.L instruction 4-7, 4-12, 4-41, A-26
addition 5-16
Index
Symbols
# 3-26, 3-38
< (forcing operator) 3-26
<< (forcing operator) 3-26
> (forcing operator) 3-26
>> (forcing operator) 3-26
A
A, see accumulator registers (A, B, C, and D)
A0, see least significant product registers (A0, B0, C0,
A1, see most significant product registers (A1, B1, C1,
A2, see extension registers (A2, B2, C2, and D2)
ABS instruction 4-3, 4-30, 4-48, A-8
accumulator data alignment 3-13
accumulator extension registers, see extension registers
accumulator least significant product registers, see least
Freescale Semiconductor
bit-manipulation operations 5-14
converting to 16-bit values 5-13
extension registers, using 5-9
notation 5-4 to 5-6, 5-9
portions, accessing 5-9
reading fractional values 5-12
reading integer data 5-12
saving and restoring 5-13
writing integer data 5-12
writing small operands 5-8
and D0)
and D1)
(A2, B2, C2, and D2)
significant product registers (A0, B0, C0, and
D0)
significant product registers (A1, B1, C1, and
D1)
5-2, 5-4 to 5-6
A-12 to A-15
Index
address registers (R0–R5) 2-8, 6-3 to 6-4
addressing mode remapping 4-12
addressing modes 3-23
AGU arithmetic instructions 4-6, 4-41
AGU registers 3-4
ALIGNSP instruction 4-7, 4-14, 4-47, 10-3, A-28
ALU, see data arithmetic logic unit (data ALU)
analog signal processing 1-5
analog-to-digital conversion 1-5 to 1-6
AND.L instruction 4-6, 4-40, A-29
AND.W instruction 4-6, 4-40, A-31
ANDC instruction 4-6, 4-11, 4-14 to 4-15, 7-1, A-33
arithmetic instructions 4-2, 4-6
arithmetic overflow 8-9
ASL instruction 4-5, 4-38, 4-48 to 4-49, A-34, A-37
ASL.W instruction 4-5, 4-38, A-34, A-37
ASL16 instruction 4-5, 4-12, 4-38, A-39
ASLA instruction 4-7, 4-12, 4-41, A-40
ASLL.L instruction 4-5, 4-38, A-41
ASLL.W instruction 4-5, 4-38, A-43
ASR instruction 4-5, 4-38, 4-48 to 4-49, A-45
ASR16 instruction 4-5, 4-12, 4-38, A-48 to A-49
ASRA instruction 4-7, 4-41, A-50
ASRAC instruction 4-5, 4-38, A-51
ASRR.L instruction 4-5, 4-38, A-53
ASRR.W instruction 4-5, 4-39, A-55
B
B, see accumulator registers (A, B, C, and D)
B0, see least significant product registers (A0, B0, C0,
B1, see most significant product registers (A1, B1, C1,
B2, see extension registers (A2, B2, C2, and D2)
fractional 5-16 to 5-17
integer 5-16 to 5-17
absolute 3-41
address register indirect 3-28
immediate 3-38
implicit 3-45
linear 6-20
modulo 6-20
post-update 3-30 to 3-32
register direct 3-28
capabilities 6-6
data alignment 3-14
restrictions 6-6
shifting 4-41
and D0)
and D1)
Index-i