dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 189

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

The CMP.W instruction is not affected by the MAC output limiter except when the first operand is not a
register (that is, it is a memory location or an immediate value) and the second operand is X0, Y0, or Y1.
In this particular case, the calculation of the U bit might be affected if saturation occurs. No other condition
code bits are affected.
Note also that if the MAC output limiter is enabled, saturation may occur when a value is transferred from
one accumulator to another with the TFR instruction. To move a 32-bit value from one accumulator to
another without limiting when the MAC output limiter is enabled, use the SXT.L instruction.
The MAC output limiter only affects operations performed in the data ALU. It has no effect on instructions
executed in other functional blocks, such as the AGU or program controller.
5.9
The DSP56800E architecture provides three instructions that can perform rounding—RND, MACR, and
MPYR. The RND instruction simply rounds a value in the accumulator register that is specified by the
instruction, whereas the MPYR or MACR instructions perform a regular MPY or MAC operation and then
round the result. Each rounding instruction rounds the result to a single-precision value so that the value
can be stored in memory or in a 16-bit register. (Note that saturation can still occur when a rounded result
is moved to a 16-bit destination). In addition, for instructions where the destination is one of the four
accumulators, the FF0 portion of the destination accumulator (A0, B0, C0, or D0) is cleared.
The DSC core implements two types of rounding: convergent rounding and two’s-complement rounding.
In the DSP56800E, the rounding point is between bits 16 and 15 of a 36-bit value. In the A accumulator,
this point is between the A1 register’s LSB and the A0 register’s MSB. The usual rounding method rounds
up any value above one-half (that is, LSP > $8000) and rounds down any value below one-half (that is,
LSP < $8000).
The question arises as to which way the number one-half (LSP equals $8000) should be rounded. If it is
always rounded one way, the results are eventually biased in that direction. Convergent rounding solves
the problem of this boundary case by rounding down if the number is even (bit 16 equals zero) and
rounding up if the number is odd (bit 16 equals one). In contrast, two’s-complement rounding always
rounds this number up. The type of rounding is selected by the rounding bit (R) of the OMR.
Freescale Semiconductor
•
•
•
•
•
AND.W, OR.W, EOR.W
LSL.W, LSR.W, ROL.W, ROR.W,
ROL.L, ROR.L
NOT.W, CLB, SUBL
ADD.B, ADD.BP, SUB.B, SUB.BP
TST, TST.B, TST.BP, TST.W, TST.L
Rounding
When the rounding bit is modified, there is a delay of 2 instruction cycles
before the new rounding mode becomes active.
Data Arithmetic Logic Unit
NOTE:
•
•
•
•
•
AND.L, OR.L, EOR.L
SXT.B, ZXT.B, SXT.L
ADC, DIV, SBC
DEC.BP, INC.BP, NEG.BP
CMP.B, CMP.BP, CMP.L
Rounding
5-43