dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 321

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

11.4.3.2
Traditionally, processors have set a breakpoint in program memory by replacing the instruction at the
breakpoint address with an illegal instruction that causes a breakpoint exception. This technique is limiting
in that breakpoints can only be set in RAM at the beginning of an opcode and not on an operand. In
addition, breakpoints can never be set on data memory locations.
The DSP56800E Enhanced OnCE breakpoint unit provides a breakpoint unit with hardware trigger
generation blocks containing address comparators for setting breakpoints on program or data memory
accesses. Breakpoints can be set on program ROM as well as program RAM locations.
The DSP56800E Enhanced OnCE breakpoint unit includes two trigger modules, a 16-bit counter, and
combining logic to trigger breakpoints from a substantially wider variety of conditions than traditional
processors. These conditions include accessing a particular memory location or value, the occurrence of a
particular number of events, or a combination of these conditions. In response to a breakpoint trigger, the
breakpoint unit can generate an interrupt, control trace buffer or counter operation, or halt the core.
Figure 11-3 is a diagram of the breakpoint unit.
The Breakpoint Unit capabilities will be demonstrated in detail in Section 11.4.4, “Effectively Using the
Debug Port,” on page 11-13.
11.4.3.2.1
The first trigger block, shown in Figure 11-4, can be programmed for program fetches, reads, writes or
memory accesses. It can also be programmed for data memory reads, writes, or accesses. Triggering is also
possible for on-chip peripheral register accesses, since these registers are implemented as
data-memory-mapped registers.
Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
Breakpoint Unit
Trigger Blocks
Overflow or
Read/Write
DEBUGEV
instruction
saturation
Fetch
Figure 11-3. Breakpoint Unit Block Diagram
Breakpoint
Interrupt
XAB1
Trigger 1
Buffer
Trace
Start
[0:PAB]
Combining
Select
Action
Logic
[0:PAB]
Buffer
Trace
Halt
Trigger 2
CDBR/CDBW
Enhanced OnCE and the Processing States
16-Bit Counter
Output
Action
32-bit
Mask
11-9