dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 689

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

B.3.3
There are a few instructions that cause the condition codes to be calculated in an unusual or non-intuitive
way. The following subsections detail these instructions and their particular condition code calculations.
B.3.3.1
In general, V is set if the MSB of the destination operand (bit 35 for an accumulator; bit 31 for the Y
register; or bit 15 for the X0, Y0, and Y1 registers) is changed as a result of the left shift. V is cleared
otherwise. If the MAC output limiter is enabled and saturation occurs, V is set. If 32-bit condition code
mode is selected (CM = 1), V is set to the value of the E bit after the operation occurs.
C is set to the value in the MSB of the source operand prior to the shift. For accumulator registers, the
MSB is bit 35 when 36-bit condition code mode is used or bit 31 when 32-bit condition code mode is used.
For the Y register, bit 31 is used. Bit 15 is the MSB for the X0, Y0, and Y1 registers.
B.3.3.2
If 32-bit condition code mode is selected (CM = 1), N is always cleared after either the ASLL.W or
ASLL.L instructions are executed. Otherwise, it is calculated as described in Section B.2.5, “Negative Bit
(N),” if 36-bit condition code mode is being used.
B.3.3.3
The calculation of N is somewhat unusual for the ASRAC and LSRAC instructions. When the MAC
output limiter is disabled (SA = 0) and the data ALU is set to 36-bit condition code mode (CM = 0), the N
bit is obtained from bit 35. If either 32-bit condition code mode is selected or saturation is enabled, the N
bit is set based on bit 31 of the result before it passes through the MAC output limiter.
B.3.3.4
The carry bit (C) is set if all bits that are specified by the bit mask are set to one; it is cleared otherwise.
Note that all the bits in the status register can be affected by BFCHG, BFCLR, and BFSET if the
destination operand is the status register.
B.3.3.5
The carry bit (C) is set if all bits that are specified by the bit mask are cleared (set to zero). It is cleared
otherwise.
B.3.3.6
For the IMPY.W instruction, a 31-bit integer product is calculated internally, and the lowest 16 bits of this
product are stored in the destination register. When the MAC output limiter is disabled and the data ALU is
set to 36-bit condition code mode (CM = 0), the N bit is set to the value in bit 15 of the result. If either
32-bit condition code mode is selected or the MAC output limiter is enabled (SA = 1), the N bit is set to the
value in bit 30 of the internally computed result. These two values differ only when the result overflows 16
bits.
V is set if the computed result does not fit in 16 bits and is cleared otherwise, regardless of the state of the
SA and CM bits.
Freescale Semiconductor
Special Calculation Rules for Certain Instructions
ASL and ASL.W
ASLL.W and ASLL.L
ASRAC and LSRAC
BFCHG, BFCLR, BFSET, BFTSTH, and BRSET
BFTSTL and BRCLR
IMPY.W
Condition Code Calculation
B-13