dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 560

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

MPY
Operation:
+ S1 × S2 → D
S1 × S2 → D
S1 × S2 → D
Description: Multiply the two signed 16-bit source operands, and place the 32-bit fractional product in the destina-
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
A-216
Before Execution
A2
0
tion (D). Both source operands must be located in the FF1 portion of an accumulator or in X0, Y0, or
Y1. If an accumulator is used as the destination, the result is sign extended into the extension portion
(FF2) of the accumulator. If the destination is one of the 16-bit registers, only the higher 16 bits of the
fractional product are stored.
This instruction is used for multiplication of fractional data or integer data when a full 32-bit product
is required (see Section 5.3.3, “Multiplication,” on page 5-18). When the destination is a 16-bit regis-
ter, this instruction is useful only for fractional data.
MPY
Prior to execution, the 16-bit X0 register contains the value $02A0 (or fractional value 0.020507813),
the 16-bit Y0 register contains the value $0200 (or fractional value 0.015625). The contents of the des-
tination register are not important prior to execution because they have no effect on the calculated val-
ue. Execution of the MPY instruction multiplies the 16-bit signed value in the X0 register by the 16-bit
signed value in Y0 (yielding the fractional product result of $000A:8000 = 0.000320435) and stores
the result back into the A accumulator. In parallel, X0 and Y0 are updated with new values that are
fetched from the data memory, and the two address registers (R0 and R3) are post-incremented by one.
SZ — Set according to the standard definition of the SZ (parallel move)
L
E
U
N
Z
V
LF
15
— Set if limiting (parallel move) has occurred
— Set if the extended portion of the result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if result equals zero
— Always cleared
(no parallel move)
(one parallel move)
(two parallel reads)
FF00
1000
P4
14
A1
Y1
Y0,X0,A
13
P3
X0
SR
P2
12
MR
DSP56800E Core Reference Manual
P1
11
X:(R0)+,Y0
02A0
0000
0200
0300
A0
Y0
P0
10
Signed Multiply
I1
9
MPY
Assembler Syntax:
MPY
MPY
I0
8
X:(R3)+,X0
SZ
7
After Execution
6
L
A2
0
5
E
(+)S1,S2,D
S1,S2,D
S1,S2,D
U
4
CCR
000A
FF00
; multiply X0 by Y0
A1
Y1
N
3
SR
X0
2
Z
Freescale Semiconductor
(no parallel move)
V
(one parallel move)
(two parallel reads)
1
8000
0300
0288
0310
C
0
A0
Y0
MPY