dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 428

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

CLB
Operation:
If S[MSB] = 0
else
Description: Count the number of leading bits in the source operand, and place that number minus one in the desti-
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
A-84
Operation
CLB
Before Execution
A2
0
(# of leading zeros
(# of leading ones – 1) in S → D
nation. The bits to count are based on the high-order bit of the source operand: if the high-order bit is
zero, the number of zeros in the source operand (minus one) is placed in the destination. If the source
register is an accumulator, the extension portion is ignored, and only the bits in the FF10 portion are
counted. The result is not affected by the state of the saturation bit (SA). This instruction is used in
conjunction with the ASLL.L instruction to normalize a number.
CLB
The A register initially contains the value $F:D7B2:4836, and the X0 register contains $AAAA. After
the CLB A,X0 instruction is executed, the value $0001 is placed in X0, since there are two leading
ones in the value contained in A10. In order to normalize A, this instruction may be followed by the
operation ASLL.L X0,A (the resulting normalized number would be $F:AF64:906C).
N
Z
V
LF
15
— Set if the high-order bit of the result is set
— Set if the result is zero
— Always cleared
D7B2
A1
P4
14
A,X0
13
P3
SR
Operands
X0
FFF,EEE
–
P2
12
1
MR
)
in S → D
DSP56800E Core Reference Manual
P1
11
7FFF
030F
4836
A0
Count Leading Bits
P0
10
I1
9
C
1
Assembler Syntax:
I0
8
W
1
; count leading bits in A, placing
; result minus one in X0
SZ
7
Count leading bits (minus one); designed to operate
with the ASLL and ASRR instructions
After Execution
A2
6
L
0
5
E
CLB
D7B2
U
4
CCR
A1
N
3
S,D
SR
Comments
X0
2
Z
Freescale Semiconductor
(no parallel move)
V
1
4836
0001
0301
A0
C
0
CLB