dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 387

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

ASLL.W
Operation:
S1 << S2 → D
D << S →
Description: This instruction can have two or three operands. It arithmetically shifts the source operand S1 or D to
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Freescale Semiconductor
Before Execution
A2
0
D
the left by the value contained in the lowest 4 bits of either S2 or S, respectively (or by an immediate
integer), and stores the result in the destination (D) with zeros shifted into the LSB. The shift count can
be a 4-bit positive integer, a value in a 16-bit register, or the MSP of an accumulator. For 36- and 32-bit
destinations, only the MSP is shifted and the LSP is cleared, with sign extension from bit 31 (the FF2
portion is ignored). The result is not affected by the state of the saturation bit (SA).
ASLL.W Y1,X0,A
Prior to execution, the Y1 register contains the value to be shifted ($AAAA), and the least significant
4 bits of the X0 register contain the amount by which to shift ($4). The contents of the destination reg-
ister are not important prior to execution because they have no effect on the calculated value. The
ASLL.W instruction arithmetically shifts the value $AAAA by 4 bits to the left and places the result
in the destination register A. Since the destination is an accumulator, the extension word (A2) is filled
with sign extension, and the LSP (A0) is cleared.
N
Z
If the CM bit is set, N is cleared. When the destination is a 16-bit register, condition codes are based
on the 16-bit result.
LF
15
— Set if MSB of result is set
— Set if result equals zero
AAAA
(no parallel move)
(no parallel move)
3456
A1
Y1
P4
14
Multi-Bit Arithmetic Left Shift Word
13
P3
X0
SR
P2
12
MR
P1
11
; shift Y1 left by amount in X0 and store in A
3456
8000
0014
0300
A0
Y0
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
ASLL.W
ASLL.W
I0
8
SZ
7
After Execution
A2
6
L
F
5
E
S1,S2,D
S,D
AAAA
AAA0
U
4
CCR
A1
Y1
N
3
X0
SR
2
Z
V
(no parallel move)
(no parallel move)
1
0000
8000
0014
0308
ASLL.W
A0
Y0
C
0
A-43