dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 267

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Chapter 9
Processing States
The DSP56800E core has six processing states, and it is always in one of these states. The states reflect the
variety of operating modes that are available to a DSP56800E device, which include low-power and debug
capabilities. The processing states are:
These processing states are available when programs are executed normally from program memory and
when instructions are fetched from data memory (see Section 8.6, “Executing Programs from Data
Memory,” on page 8-23). Each of these processing states is considered in the following pages.
9.1
The normal processing state is the typical state of the processor, where it performs normal instruction
execution. The core enters the normal processing state after reset, if debugging is not active.
Additional information on the normal processing state can be found in Section 10.2, “Normal Pipeline
Operation,” on page 10-3.
9.2
The processor enters the reset processing state when a hardware reset signal is asserted. The core is held in
reset during power up through the assertion of the RESET terminal, making this the first processing state
entered by the DSC.
The reset processing state takes precedence over all other processing states. When the reset terminal to the
core is asserted, the core exits the processing state it was in previously and immediately enters the reset
processing state.
Freescale Semiconductor
•
•
•
•
•
•
Normal—the normal instruction execution state.
Reset—the state where the core is forced into a known reset state. The first program instruction is
fetched upon exiting this state.
Exception—the interrupt processing state, where the core transfers program control from its current
location to an interrupt service routine using the interrupt vector table.
Wait—a low-power state where the core is shut down but the peripherals and interrupts remain
active.
Stop—a low-power state where the core, interrupts, and selected peripherals are shut down.
Debug—a debugging state where the core is halted and the Enhanced On-Chip Emulation
(Enhanced OnCE) module is enabled and used for debug activity.
Normal Processing State
Reset Processing State
Processing States
9-1