dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 610

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

SUB
Operation:
D – S →
D – S →
D – S →
Description: Subtract the source register from the destination register and store the result in the destination (D). If
Usage:
Example 1:
Explanation of Example:
A-266
Before Execution
A2
D
D
D
4
the destination is a 36-bit accumulator, 16-bit source registers are first sign extended internally and
concatenated with 16 zero bits to form a 36-bit operand (the Y register is only sign extended). When
the destination is X0, Y0, or Y1, 16-bit subtraction is performed. In this case, if the source operand is
one of the four accumulators; the FF1 portion (properly sign extended) is used in the 16-bit subtraction
(the FF2 and FF0 portions are ignored). Similarly, if the destination is the Y register, the FF2 portion
is ignored.
This instruction can be used for both integer and fractional two’s-complement data.
SUB
Prior to execution, the 16-bit Y0 register contains the negative value $8003, and the 36-bit A accumu-
lator contains the value $4:8058:1234. The SUB instruction automatically appends the 16-bit value in
the Y0 register with 16 LS zeros, sign extends the resulting 32-bit long word to 36 bits. This value is
then subtracted from the 36-bit A accumulator. Thus, 16-bit operands are always subtracted from the
MSP of A or B (A1 or B1) with the results correctly extending into the extension register (A2 or B2).
(no parallel move)
(one parallel move)
(two parallel reads)
8058
2000
A1
Y1
Y0,A
SR
DSP56800E Core Reference Manual
X:(R2)+N,Y1 ; 36-bit subtract, load Y1, update R2
1234
8003
0300
A0
Y0
Subtract
SUB
Assembler Syntax:
SUB
SUB
After Execution
A2
5
S,D
S,D
S,D
4FFF
0055
A1
Y1
(no parallel move)
(one parallel move)
(two parallel reads)
SR
Freescale Semiconductor
1234
8003
0331
A0
Y0
SUB