dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 167

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

DSP56800E assembler automatically rearranges the source operands for the following operations if they
are not specified in the required order:
This re-ordering by the assembler has no impact on the execution of the instruction. Note, however, that
the instruction dis-assembles as the re-ordered version. For example:
This instruction specifies the two source operands in the wrong order (the X0 register cannot be specified
as the first operand). The assembler replaces this instruction with the following:
This instruction performs the same function, but with the operands in the proper order. Note that the
instruction always dis-assembles with the second ordering of operands.
5.3.4
Fractional and integer division of both positive and signed values is supported using the DIV instruction.
The DIV instruction performs a single division iteration, calculating 1 bit of the result with each execution.
The dividend (numerator) is a 32-bit fractional or 31-bit integer value, and the divisor (denominator) is a
16-bit fractional or integer value. A full division requires that the DIV instruction be executed 16 times.
Algorithms for performing division can vary, depending on the values being divided and whether or not
the remainder after integer division must also be calculated. To formulate the correct approach, consider
the following key questions:
Once you answer these questions, select the appropriate division algorithm. The most general division
algorithms are the fractional and integer algorithms for four-quadrant division,
quotient and a remainder. These algorithms require the most time to complete and use the most registers.
Simpler, quicker algorithms can be used when positive numbers are divided or when the remainder is not
required. Note that none of the algorithms that are presented here apply to extended-precision division,
which requires more than 16 quotient bits.
Freescale Semiconductor
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1. Four-quadrant division is so called because it generates correct results for any combination of positive or negative dividends and divisors.
Are both operands always guaranteed to be positive?
Are operands fractional or integer?
Is the quotient all that is needed, or is the remainder needed as well?
Will the calculated quotient fit in 16 bits in integer division?
Are the operands signed or unsigned?
How many bits of precision are in the dividend?
What about overflow in fractional and integer division?
Will there be “integer division” effects?
Division
MAC S1,S2,D
MACR S1,S2,D
MPY S1,S2,D
MPYR S1,S2,D
MPY
MPY
-X0,Y1,A
-Y1,X0,A
MAC –S1,S2,D
MACR –S1,S2,D
MPY –S1,S2,D
MPYR –S1,S2,D
Data Arithmetic Logic Unit
; X0 specified as first source operand
; Y1 specified as first source operand
IMAC.L S1,S2,D
IMPY.L S1,S2,D
IMPY.W S1,S2,D
Fractional and Integer Arithmetic
1
which generate both a
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