dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 467

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

DIV
Operation:
(see following figure)
Description: This instruction is a divide iteration that is used to calculate 1 bit of the result of a division. After the
Freescale Semiconductor
If
correct number of iterations, this instruction will divide the destination operand (D)—dividend or nu-
merator—by the source operand (S)—divisor or denominator—and store the result in the destination
accumulator. The 32-bit dividend must be a positive value that is correctly sign extended to 36 bits and
that is stored in the full 36-bit destination accumulator. The 16-bit divisor is a signed value and is
stored in the source operand. (The division of signed numbers is handled using the techniques docu-
mented in Section 5.3.4, “Division,” on page 5-21.) This instruction can be used for both integer and
fractional division. Each DIV iteration calculates 1 quotient bit using a non-restoring division algo-
rithm (see the description that follows). After the execution of the first DIV instruction, the destination
operand holds both the partial remainder and the formed quotient. The partial remainder occupies the
high-order portion of the destination accumulator and is a signed fraction. The formed quotient occu-
pies the low-order portion of the destination accumulator (A0 or B0, C0, or D0) and is a positive frac-
tion. One bit of the formed quotient is shifted into the LSB of the destination accumulator at the start
of each DIV iteration. The formed quotient is the true quotient if the true quotient is positive. If the true
quotient is negative, the formed quotient must be negated. For fractional division, valid results are ob-
tained only when |D| < |S|. This condition ensures that the magnitude of the quotient is less than one
(that is, it is fractional) and precludes division by zero.
The DIV instruction calculates 1 quotient bit based on the divisor and the previous partial remainder.
To produce an N-bit quotient, the DIV instruction is executed N times, where N is the number of bits
of precision that is desired in the quotient (1 < N < 16). Thus, for a full-precision (16-bit) quotient,
16 DIV iterations are required. In general, executing the DIV instruction N times produces an N-bit
quotient and a 32-bit remainder, which has (32 – N) bits of precision and whose N MSBs are zeros.
The partial remainder is not a true remainder and must be corrected (due to the non-restoring nature of
the division algorithm) before it may be used. Therefore, once the divide is complete, it is necessary
to reverse the last DIV operation and restore the remainder to obtain the true remainder. The result is
not affected by the state of the saturation bit (SA).
The DIV instruction uses a non-restoring division algorithm that consists of the following operations:
1. Compare the source and destination operand sign bits. An exclusive OR operation is performed on
2. Shift the partial remainder and the quotient. The 36-bit destination accumulator is shifted 1 bit to the
D[35] ⊕ S[15] = 1
bit 35 of the destination operand and bit 15 of the source operand.
left. C is moved into the LSB (bit 0) of the accumulator.
Then
Else
D2
D2
D1
D1
Instruction Set Details
Divide Iteration
Assembler Syntax:
DIV
D0
D0
S,D
C;
C;
(no parallel move)
D1 + S
D1 – S
D1
D1
DIV
A-123