dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 700

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

integer addition 5-16 to 5-17
integer arithmetic 5-19
integer data types 3-5
integer multiplication 5-18 to 5-19
interrupt arbitration unit 8-3
interrupt controller 8-3, 9-3, 9-10 to 9-12, 10-7, 10-9
interrupt mask bits (I1 and I0) 8-10, 9-2
interrupt priority level (IPL) 8-7, 8-10
interrupt processing 10-7
interrupt vector table 8-15, 9-8
interrupts 8-18 to 8-19, 8-25 to 8-26, 8-28, 9-2 to 9-3
IP-BUS 2-4 to 2-5
IPL, see interrupt priority level (IPL)
J
Jcc instruction 4-10, 4-14, 4-45, 9-10, A-159
JMP instruction 4-10, 4-14, 4-45, 8-26, A-161
JMPD instruction 4-10, 4-13 to 4-14, 4-45, A-162
Joint Test Action Group (JTAG) 11-1, 11-4
JR1CLR operation 7-10
JR1SET operation 7-10
JRCLR operation 7-8 to 7-9
JRSET operation 7-8 to 7-9
JSR instruction 4-10, 4-14, 4-45, 8-11, 8-15, 9-5,
JTAG and OnCE port pinout 11-28
JTAG, see Joint Test Action Group (JTAG)
L
L, see limit bit (L)
LA, see loop address register (LA)
LA2, see loop address register 2 (LA2)
Late Execution state 10-5
LC, see loop count register (LC)
LC2, see loop count register 2 (LC2)
least significant product registers (A0, B0, C0, and
LF, see loop flag bit (LF)
limit bit (L) 8-10
linear addressing 6-20
local variables 8-16 to 8-17
logic unit 5-5
logical instructions 4-6, 4-40, 5-25
long-word data alignment 3-17, 3-19, 9-9
Index-iv
pipeline 10-1
fast 9-6
normal 9-5
latency 10-7, 10-22
sources
hardware 9-8
hardware stack overflow 9-9
illegal instruction 9-8
misaligned data access 9-9
A-163
D0) 3-2 to 3-3, 5-4, 5-9
DSP56800E Core Reference Manual
loop address register (LA) 2-9, 8-4, 8-12
loop address register 2 (LA2) 2-9, 8-4
loop count register (LC) 2-9, 8-4, 8-11 to 8-12
loop count register 2 (LC2) 2-9, 8-4, 8-11
loop flag bit (LF) 8-11
looping
looping control unit 8-3
LSL.W instruction 4-5, 4-39, A-164
LSR.W instruction 4-5, 4-39, A-166
LSR16 instruction 4-5, 4-12, 4-39, A-168
LSRA instruction 4-7, 4-42, A-169
LSRAC instruction 4-5, 4-39, A-170
LSRR.L instruction 4-5, 4-39, A-172
LSRR.W instruction 4-5, 4-39, A-174
M
M01, see modifier register (M01)
MA, see operating mode bits (MB and MA)
MAC instruction 4-2, 4-15, 4-28, 4-48 to 4-49, A-176
MAC output limiter 2-8, 5-2, 5-39, 5-41 to 5-43, 8-6
MACR instruction 4-2, 4-28, 4-48 to 4-49, 5-43, 8-6,
MACSU instruction 4-2, 4-30, 5-28, A-182
MB, see operating mode bits (MB and MA)
memory
memory map 8-4
mode register (MR) 8-7
modifier register (M01) 2-9, 6-3, 6-5, 6-20 to 6-22,
modulo address arithmetic 6-3
modulo addressing 6-20
most significant product registers (A1, B1, C1, and
move instructions 4-8, 4-27, 4-50
MOVE.B instruction 4-9, 4-21, 4-25, A-184
MOVE.BP instruction 4-9, 4-20 to 4-21, 4-25, A-187
MOVE.L instruction 4-9, 4-22, 4-25 to 4-27, A-191
MOVE.W instruction 4-9, 4-23 to 4-28, 4-49, A-198
MOVEU.B instruction 4-9, 4-21, 4-25, A-207
instructions 4-8, 4-46
termination 8-20
architecture 2-4, 8-6
data alignment 3-15
symbols (X: and P:) 3-9
addressing modes supported 6-29
bank wrapping 6-33
memory accesses
overview 6-20
programming the M01 register 6-22
setting up 6-32
side effects 6-34
A-179
9-2
byte 6-22
long word 6-24
word 6-23
D1) 3-2 to 3-3, 5-4, 5-9
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