dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 339

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

11.5
The DSP56800E core Joint Test Action Group (JTAG) test access port (TAP) provides the interface for the
Enhanced OnCE module to the DSC JTAG pins. This TAP controller is designed to be incorporated into a
chip multi–JTAG TAP Linking Module (JTAG TLM) system. The JTAG TLM is a dedicated,
user-accessible, test access port (TAP) system that is compatible with the IEEE Standard 1149.1a-1993,
IEEE Standard Test Access Port and Boundary-Scan Architecture. Problems associated with testing
high-density circuit boards have led to the development of this standard under the sponsorship of the Test
Technology Committee of IEEE and the JTAG. If the core TAP is not incorporated into a JTAG TLM
system it will not be compliant with the IEEE 1149.1a-1993 standard, but the TAP will still serve as an
interface to the core Enhanced OnCE module. Specific details on the implementation of the JTAG port for
a given DSP56800E–based device are provided in the user’s manual for that device.
11.5.1
The DSP56800E JTAG port has the following capabilities:
The following sections provide an overview of the port’s architecture and commands.
11.5.2
The JTAG port consists of the following components:
The serial interface provides the communication link between the core and the host development or debug
system. All JTAG data is sent over this interface. Enhanced OnCE commands and data from the host
system can also sent over this interface if accessed via JTAG. It is implemented as a serial interface to
occupy as few external pins on the device as possible. For a full description of the interface signals, consult
the user’s manual for the specific device.
Commands sent to the JTAG module are decoded and processed by the command decoder. Commands for
the JTAG port are completely independent from the DSP56800E instruction set, and they are executed in
parallel by the JTAG logic.
The JTAG module contains the DSP56800E identification register, which provides a unique ID for each
revision of the DSP56800E core. This register enables a development system to determine the
manufacturer, process technology, part, and revision numbers of the DSP56800E core via the JTAG port.
Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
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Provides queried identification information for the DSP56800E core (manufacturer, technology
process, part, and version numbers)
Provides a means of accessing the Enhanced OnCE module controller and circuits to control a target
system
Provides a means of entering the debug mode of operation
Bypasses the TAP through a single-bit register in the Shift-DR-Scan path
Serial communication interface
Command decoder and interpreter
DSP56800E identification register
JTAG Port
JTAG Capabilities
JTAG Port Architecture
JTAG Port
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