dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 278

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Processing States
Wait mode is exited when an interrupt request is sent to the core. The interrupt must be enabled
(unmasked) and must be at a higher priority level than the core’s current interrupt priority level, as defined
by the I1 and I0 bits in the status register. Upon exiting this mode, the program continues execution in the
exception processing state, where it processes the recognized interrupt request. Wait mode is also exited
when the chip is reset, or by certain debug actions in the JTAG/Enhanced OnCE unit.
9.4.1
The timing for entering and exiting the wait processing state is determined by the architecture of the
particular DSP56800E–based device being used. Consult that device’s user’s manual for exact wait mode
timing information.
9.4.2
The DSP56800E core supports the permanent disabling of the wait processing state. If disabled, wait mode
can never be entered, and the WAIT instruction simply executes five NOPs. Upon completing the NOP
cycles, program execution continues with the instruction that immediately follows the WAIT instruction.
Consult the specific DSP56800E–based device’s user’s manual for more information on disabling wait
mode.
9.5
The second of the DSP56800E core’s low-power-consumption states is stop mode. In this state the core
consumes the lowest amount of power. This mode is entered by executing the STOP instruction. After a
delay, the internal core clock, the interrupt controller, and any on-chip memories are disabled. The clock is
also disabled to selected peripherals on the chip, but it may continue to run to the PLL block or to a timer
block.
All peripheral and external interrupts are typically cleared on entering the stop state. Hardware stack
overflows that were pending remain pending. The priority levels of the peripherals remain as they were
before the STOP instruction was executed. The on-chip peripherals are held in their respective individual
reset states.
In a typical system architecture, the following events can bring the core out of the stop processing state:
Any of these actions will re-activate the oscillator, and, after a clock stabilization delay, clocks to the
processor and peripherals will be re-enabled. The clock stabilization delay period is determined by the stop
delay (SD) bit in the operating mode register (OMR).
If an interrupt is used to wake the processor from stop mode, the first code to be executed on leaving stop
mode is either the interrupt handler for that request or the instruction immediately following the STOP
instruction (see the user’s manual for a particular DSP56800E–based device for more details). Likewise,
the processor will enter the reset processing state if a reset signal was the cause for waking from stop
mode.
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An external pin is asserted.
The RESET signal is asserted.
An on-chip timer reaches zero.
Debug actions in the JTAG/Enhanced OnCE unit occur.
Stop Processing State
Wait Mode Timing
Disabling Wait Mode
DSP56800E Core Reference Manual
Freescale Semiconductor