dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 143

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
ENDDO
REP
ALIGNSP
DEBUGEV
DEBUGHLT
ILLEGAL
NOP
STOP
SWI
SWI
SWILP
WAIT
Operation
Operation
Operands
Operands
#<0–63>
DDDDD
#<0–2>
Table 4-39. Looping Instructions (Continued)
C
3
3
3
4
1
1
4
1
*
*
Table 4-40. Control Instructions
C
1
2
5
Instruction Set Introduction
W
1
1
1
1
1
1
1
1
1
1
W
1
1
1
Save SP to the stack and align SP for long memory accesses, point-
Generate a debug event.
Enter the debug processing state.
Generate an illegal instruction exception; can be used to verify inter-
No operation.
Enter stop low-power mode.
Generate an interrupt at the highest priority level (level 3,
Enter wait low-power mode.
ing to an empty location.
rupt handlers for illegal instructions.
The number of cycles is dependent upon chip implementation.
Generate an interrupt at priority level 0, 1, or 2 as specified by the
instruction.
non-maskable).
Generate an interrupt at the lowest priority level (lower than level 0).
The number of cycles is dependent upon chip implementation.
Remove one value from the hardware stack and update the NL
and LF bits appropriately.
Note:
Hardware repeat of a 1-word instruction with immediate loop
count.
Hardware repeat of a 1-word instruction with loop count specified
in register.
If LC is not equal to zero, start hardware REP loop with 16-bit loop
count in register. Otherwise skip body of loop (adds 1 additional
cycle).
Any register is allowed except C2, D2, C0, D0,
C, D, Y, M01, N3, LA, LA2, LC, LC2, SR, OMR, and HWS.
When looping with a value in an accumuator, use A1, B1, C1, or
D1 to avoid saturation when reading the accumulator.
Does not branch to the end of the loop.
Comments
Comments
Instruction Set Summary
4-47