dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 313

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Chapter 11
JTAG and Enhanced On-Chip
Emulation (Enhanced OnCE)
The DSP56800E Family includes extensive integrated support for application software development and
real-time debugging. Two modules, the Enhanced On-Chip Emulation module (Enhanced OnCE) and the
core test access port (TAP, commonly called the JTAG port), work together to provide these capabilities.
Both are accessed through a common JTAG/Enhanced OnCE interface. Using these modules allows the
user to insert the DSC chip into a target system while retaining debug control. This capability is especially
important for devices without an external bus, since it eliminates the need for a costly cable to bring out the
footprint of the chip, as is required by a traditional emulator system.
The DSP56800E Enhanced OnCE module is a Freescale-designed module that is used to develop and
debug application software used with the chip. This module allows non-intrusive interaction with the DSC
and is accessible either through the pins of the JTAG interface or by software program control of the
DSP56800E core. Among the many features of the Enhanced OnCE module is the support for data
communication between the DSC chip and the host software development and debug systems in real-time
program execution. Other features allow for hardware breakpoints, the monitoring and tracking of program
execution, and the ability to examine and modify the contents of registers, memory, and on-chip
peripherals, all in a special debug environment. No user-accessible resources need to be sacrificed to
perform debugging operations.
The DSP56800E JTAG port is used to provide an interface for the Enhanced OnCE module to the DSC
JTAG pins. This TAP controller is designed to be incorporated into a chip multi–JTAG TAP Linking
Module (JTAG TLM) system. The JTAG TLM is a dedicated, user-accessible, test access port (TAP)
system that is compatible with the IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and
Boundary-Scan Architecture.
This chapter presents an overview of the capabilities of the JTAG and Enhanced OnCE modules. Because
their operation is dependent upon the architecture of a specific DSP56800E device, the exact
implementation is necessarily device dependent.
11.1
Enhanced OnCE Module
The Enhanced OnCE module provides emulation and debug capability directly on the chip, eliminating the
need for expensive and complicated stand-alone in-circuit emulators (ICEs). The Enhanced OnCE module
permits full-speed, non-intrusive emulation on a user’s target system. This section describes the Enhanced
OnCE emulation environment for use in debugging real-time embedded applications.
Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
11-1