dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 39

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Chapter 2
Core Architecture Overview
This chapter presents the core’s architecture and programming model as well as the overall system
architecture for devices based on the DSP56800E core. It introduces the different blocks and data paths
within the core and their functions. More detailed information on the individual blocks within the core,
such as the data ALU, AGU, and program controller, appears in later chapters.
2.1
The DSP56800E core architecture extends Freescale’s DSP56800 Family architecture. It is source-code
compatible with DSP56800 devices and adds the following new features:
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Byte and long data types, supplementing the DSP56800’s word data type
24-bit data memory address space
21-bit program memory address space
Three additional 24-bit pointer registers (one of which can be used as an offset register)
A secondary 16-bit offset register to further enhance the dual parallel data ALU instructions
Two additional 36-bit accumulator registers
Full-precision integer multiplication
32-bit logical and shifting operations
Second read in dual read instruction can access off-chip memory
Loop count (LC) register extended to 16 bits
Full support for nested DO looping through additional loop address and count registers
Loop address and hardware stack extended to 24 bits
Three additional interrupt levels with a software interrupt for each level
Enhanced On-Chip Emulation (Enhanced OnCE) with three debugging modes:
— Non-intrusive real-time debugging
— Minimally intrusive real-time debugging
— Breakpoint and step mode (core is halted)
Extending DSP56800 Architecture
Core Architecture Overview
2-1