dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 37

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

The DSP56800E Family is not a custom IC designed for a particular application; it is designed as a
general-purpose DSC architecture to efficiently execute common DSC algorithms and controller code in
minimal time.
As Figure 1-5 shows, the key attributes of a DSC are as follows:
The multiply-accumulate (MAC) operation is the fundamental operation used in DSC. The DSP56800E
family of processors has a dual Harvard architecture that is optimized for MAC operations. Figure 1-5
shows how the DSP56800E architecture matches the shape of the MAC operation. The two operands, C()
and X(), are directed to a multiply operation, and the result is summed. This process is built into the chip in
that two separate data memory accesses are allowed to feed a single-cycle MAC. The entire process must
occur under program control to direct the correct operands to the multiplier and to save the accumulated
result, as needed. Since the memory and the MAC are independent, the DSC can perform two memory
moves, a multiply and an accumulate, and two address updates in a single operation. As a result, many
DSC benchmarks execute very efficiently for a single-multiplier architecture.
Freescale Semiconductor
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Wide range of applications
Filters with sharper filtering characteristics
High noise immunity
Adaptive filters are easily implemented
Self-test can be built in
Better power-supply rejection
Multiply-accumulate (MAC) operation
Fetching up to two operands per instruction cycle for the MAC
Flexibility in implementation through a powerful instruction set
Input/output capability to move data in and out of the DSC
Figure 1-5. Mapping DSC Algorithms into Hardware
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