dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 406

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

BFCLR
Operation:
0 →(<bitfield> of destination) (no parallel move)
Description: Test all selected bits of the destination operand. If all selected bits are set, C is set; otherwise, C is
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Note:
A-62
cleared. Then clear the selected bits, and store the result in the destination. A 16-bit immediate value
is used to specify which bits are tested and cleared. Those bits that are set in the immediate value are
the same bits that are tested and cleared in the destination; those bits that are cleared in the immediate
value are ignored in the destination. This instruction performs a read-modify-write operation on the
destination memory location or register and requires two destination accesses.
This instruction is very useful in performing I/O and flag bit manipulation.
BFCLR
Prior to execution, the 16-bit X memory location X:$5000 contains the value $7FF5. Execution of the
BFCLR instruction tests the state of bits 4, 8, and 9 in X:5000, sets the C bit (because all the selected
bits were set), and then clears the selected bits.
For destination operand SR:
For other destination operands:
L
C
If all bits in the mask are cleared, the instruction executes two NOPs and sets the C bit.
Before Execution
X:$5000
LF
15
— Set if data limiting occurred during 36-bit source move
— Set if all bits specified by the mask are set
SR
P4
14
For this destination only, the C bit is not updated as is done for all other destination operands.
All SR bits except bits 14–10 are updated with values from the bitfield unit.
Bits 14–10 of the mask operand must be cleared.
Cleared if at least 1 bit specified by the mask is not set
#$0310,X:$5000
13
P3
P2
12
7FF5
0300
MR
DSP56800E Core Reference Manual
P1
11
Test Bitfield and Clear
P0
10
I1
9
Assembler Syntax:
BFCLR
BFCLR
I0
8
; test and clear bits 4, 8, and 9 in
; an on-chip peripheral register
SZ
7
6
L
5
E
After Execution
X:$5000
#iiii,X:<ea>
#iiii,D
U
4
CCR
SR
N
3
2
Z
7CE5
0301
Freescale Semiconductor
V
(no parallel move)
(no parallel move)
1
C
0
BFCLR