dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 248

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Program Controller
8.2.2.6
The extension in use (E) bit is cleared if the high-order 5 bits (bits 35–31) of a 36-bit result are the same
(00000 or 11111). Otherwise, this bit is set.
When the high-order 5 bits all contain the same value, the extension portion of an accumulator (bits 35–32)
just holds sign extension and can be ignored. When they are not all the same, the bits in the extension
register are significant and must be considered when additional computations are performed or when the
accumulator is written to memory.
This bit is not affected by the OMR’s CM bit.
8.2.2.7
The limit (L) bit is a latching bit (sticky bit) that is set if the overflow bit is set or if the data limiters
perform a limiting operation. It is not affected otherwise. The L bit is cleared only by a processor reset or
by an instruction that specifically clears it.
8.2.2.8
The size (SZ) bit is a latching bit (sticky bit) that indicates that word growth is occurring in an algorithm.
The bit is set when a 36-bit accumulator is moved to data memory and bits 30 and 29 of the source
accumulator are not the same. The setting of the SZ bit occurs via the following computation:
This bit is especially useful for attaining maximum accuracy when a block-floating-point fast Fourier
transform (FFT) is performed. See the application note Implementation of Fast Fourier Transforms on
Freescale’s Digital Signal Processors (document order number APR4/D) for information on
implementing FFT algorithms on the DSP56800E.
The SZ bit is cleared only by a processor reset or by an instruction that specifically clears it.
8.2.2.9
The interrupt mask (I1 and I0) bits set the interrupt priority level (IPL) that is needed for an interrupt
source to interrupt the processor. The current priority level of the processor may be changed under
software control. Both interrupt mask bits are set to one during processor reset. Table 8-3 shows the
exceptions that are permitted and masked for the various settings of I1 and I0.
Exception processing is explained in detail in Section 9.3, “Exception Processing State,” on page 9-2.
8-10
SZ = SZ | (Bit 30 ⊕ Bit 29)
Extension in Use (E)—Bit 5
Limit (L)—Bit 6
Size (SZ)—Bit 7
Interrupt Mask (I0–I1)—Bits 8–9
I1
0
0
1
1
I0
0
1
0
1
Table 8-3. Interrupt Mask Bits Settings
DSP56800E Core Reference Manual
Exceptions Permitted
IPL 0, 1, 2, 3, LP
IPL 1, 2, 3
IPL 2, 3
IPL 3
Exceptions Masked
IPL 0, 1, 2
IPL 0, 1
None
IPL 0
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