dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 516

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

LSRR.L
Operation:
If S[15] = 0 or S is not a register,
D >> S →
Else
D << –S → D
Description: Logically shift the second operand to the right by the value contained in the 5 lowest bits of the first
Example:
Explanation of Example:
Condition Codes Affected:
Note:
A-172
Before Execution
A2
F
D
operand (or by an immediate integer), and store the result back in the destination (D). The shift count
can be a 5-bit positive immediate integer or the value contained in X0, Y0, Y1, or the MSP of an ac-
cumulator. For 36- and 32-bit destinations, the MSP:LSP are shifted, with zero extension from bit 31
(the FF2 portion is ignored). If the shift count in a register is negative (bit 15 is set), the direction of
the shift is reversed. The result is not affected by the state of the saturation bit (SA).
LSRR.L Y1,A
Prior to execution, the A accumulator contains the value to be shifted, $F:F123:3456, and the Y1 reg-
ister contains the amount by which to shift ($10 = 16). The LSRR.L instruction logically shifts the des-
tination accumulator 16 bits to the right and places the result back in A.
N
Z
Condition code results are set according to the size of the destination operand.
LF
15
— Set if the MSB of the result is set
— Set if the result equals zero
(no parallel move)
(no parallel move)
F123
0010
A1
Y1
P4
14
13
P3
SR
Multi-Bit Logical Right Shift Long
P2
12
MR
DSP56800E Core Reference Manual
P1
11
3456
8000
0300
A0
Y0
P0
10
; left shift 32-bit A10 by Y1
I1
9
Assembler Syntax:
LSRR.L
LSRR.L
I0
8
SZ
7
After Execution
A2
6
L
0
5
E
S,D
S,D
U
4
0000
0010
CCR
A1
Y1
N
3
SR
2
Z
Freescale Semiconductor
V
(no parallel move)
(no parallel move)
1
F123
8000
0300
A0
Y0
C
0
LSRR.L