dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 389

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

ASR
Operation:
(see following figure)
Description: Arithmetically shift the destination operand (D) 1 bit to the right and store the result in the destination
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Freescale Semiconductor
Before Execution
B2
8
accumulator. The LSB of the destination prior to the execution of the instruction is shifted into C, and
the MSB of the destination is held constant. When the destination register is Y or a 16-bit register, the
MSB is bit 31 or bit 15, respectively. A duplicate destination is not allowed when ASR is used in con-
junction with a parallel read.
ASR
Prior to execution, the 36-bit B accumulator contains the value $8:AAAA:AAAA. Execution of the
ASR instruction shifts the 36-bit value in the B accumulator 1 bit to the right and stores the result back
in the B accumulator. C is cleared by the operation because bit 0 of A was cleared prior to the execution
of the instruction. The N bit of CCR (bit 3) is set because bit 35 of the result in A is set. The E bit of
CCR (bit 5) is set because the extension portion of B is used by the result.
SZ — Set according to the standard definition of the SZ bit (parallel move)
L
E
U
N
Z
V
C
Condition code results depend on the size of the destination operand.
MSB
LF
15
— Set if data limiting has occurred during parallel move
— Set if the extension portion of result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if result equals zero
— Always cleared
— Set if bit 0 of source operand was set prior to the execution of the instruction
AAAA
P4
14
B1
D2
B
13
P3
SR
P2
12
MR
D1
P1
11
Arithmetic Shift Right
X:(R3)+,Y0; divide B by 2, load Y0, and update R3
AAAA
0300
B0
P0
10
Instruction Set Details
I1
9
Assembler Syntax:
ASR
ASR
ASR
I0
8
D0
SZ
7
After Execution
6
L
B2
C
5
E
D
D
D
C
U
4
CCR
5555
B1
N
3
(no parallel move)
(one parallel move)
(two parallel reads)
(parallel move)
SR
2
Z
V
1
5555
0328
C
0
B0
ASR
A-45