dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 520

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

MAC
Operation:
D + (S1 × S2) → D (no parallel move)
D + (S1 × S2) → D (one parallel move)
D + (S1 × S2) → D (two parallel reads)
Description: Multiply the two signed 16-bit source operands, and add or subtract the 32-bit fractional product to or
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
A-176
Before Execution
A2
0
from the destination (D). Both source operands must be located in the FF1 portion of an accumulator
or in X0, Y0, or Y1. The fractional product is first sign extended before the 36-bit addition (or subtrac-
tion) is performed. If the destination is one of the 16-bit registers, it is first sign extended internally and
concatenated with 16 zero bits to form a 36-bit operand before the operation to the fractional product;
the high-order 16 bits of the result are then stored.
This instruction is used for the multiplication and accumulation of fractional data or integer data when
a full 32-bit product is required (see Section 5.3.3, “Multiplication,” on page 5-18). When the destina-
tion is a 16-bit register, this instruction is useful only for fractional data.
MAC
Prior to execution, the 16-bit X0 register contains the value $0280 (or fractional value 0.019531250),
the 16-bit Y0 register contains the value $0200 (or fractional value 0.015625), and the 36-bit A accu-
mulator contains the value $0:0000:8000 (or fractional value 0.000015259). Execution of the MAC
instruction multiplies the 16-bit signed value in the X0 register by the 16-bit signed value in Y0 (yield-
ing the fractional product result of $000A:0000 = 0.000305176), adds the resulting 32-bit product to
the 36-bit A accumulator, and stores the result ($0:000A:8000 = 0.00320435) back into the A accumu-
lator. In parallel, X0 and Y0 are updated with new values that are fetched from the data memory, and
the two address registers (R0 and R3) are post-incremented by one.
SZ — Set according to the standard definition of the SZ bit (parallel move)
L
E
U
N
Z
V
LF
15
— Set if limiting (parallel move) or overflow has occurred in result
— Set if the extension portion of accumulator result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if accumulator result equals zero
— Set if overflow has occurred in accumulator result
FF00
0000
P4
14
A1
Y1
Y0,X0,A
13
P3
X0
SR
P2
12
MR
DSP56800E Core Reference Manual
P1
11
X:(R0)+,Y0
Multiply-Accumulate
8000
0200
0280
0300
A0
Y0
P0
10
I1
9
Assembler Syntax:
MAC
MAC
MAC
I0
8
X:(R3)+,X0
SZ
7
After Execution
6
L
A2
0
5
E
(+)S1,S2,D
(+)S1,S2,D
S1,S2,D
U
4
CCR
000A
FF00
; fractional MAC, two reads
A1
Y1
N
3
SR
X0
2
Z
Freescale Semiconductor
(no parallel move)
(one parallel move)
V
(two parallel reads)
1
8000
0300
0288
0310
C
0
A0
Y0
MAC