dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 147

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5
Data Arithmetic Logic Unit
This chapter describes the architecture and operation of the data arithmetic logic unit (ALU).
Multiplication, arithmetic, logical, and shifting operations are performed in this block. (Note that addition
can also be performed in the address generation unit, and that the bit-manipulation unit can also perform
logical operations.)
The data ALU can perform the following operations with a throughput of 1 cycle per instruction, except
where noted:
Multiple buses within the data ALU allow complex arithmetic operations (such as a multiply-accumulate)
to execute in parallel with up to two memory transfers in a single execution cycle.
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Multiplication (with or without rounding)
Multiplication with negated product (with or without rounding)
Multiplication and accumulation (with or without rounding)
Multiplication and accumulation with negated product (with or without rounding)
Multi-precision multiplication support
Addition and subtraction
Increments and decrements (for 8-, 16-, 32-, and 36-bit operands)
Test and comparison (for 8-, 16-, 32-, and 36-bit operands)
Logical operations (AND, OR, and EOR)
One’s-complement and two’s-complement negation
Arithmetic and logical shifts
Rotates
Rounding
Absolute values
Sign extension and zero extension
Saturation (limiting) on data ALU and move operations
Conditional register moves
Division iteration
Normalization iterations (execute in 4 clock cycles)
Data Arithmetic Logic Unit
5-1