dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 272

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Processing States
When interrupt processing is complete, the interrupt routine should be terminated by an RTI or RTID
instruction. These instructions return control to the interrupted program and restore the status register to its
original value.
Normal interrupts can be nested (refer to Section 10.3.3, “Nested Interrupts,” on page 10-11).
9.3.2.2
The default implementation of fast interrupt processing in the DSP56800E core, which is available only for
level 2 interrupts, is performed when the instruction that is located in the appropriate slot in the vector table
is not a JSR. Fast interrupt processing has lower overhead than normal processing and should be used for
all low-latency or time-critical interrupts. Since the interrupt controller is external to the core, chip
implementations of this core can provide an alternate scheme in detecting fast interrupt processing. For
example, the 568xx family of chips has implemented a scheme whereas, the interrupt controller intercepts
the normal vector table processing and inserts the absolute address into the core via the VAB bus. In this
implementation, the IRQ selected for fast interrupt processing and the address of the code for the fast
interrupts are coded in special chip registers. Please refer to the specific chip implementation for complete
description of fast interrupt processing. The description of fast interrupt throughout this manual follows the
default implementation prescribed by the DSP56800E core.
Initially, fast interrupt processing resembles normal interrupt processing: the core performs steps 1–3 in
Section 9.3.2.1, “Normal Interrupt Processing,” for fast interrupt processing as well. When the core
recognizes that fast interrupt processing should be used—by determining that the interrupt is a level 2
interrupt and that the instruction in the vector is not a JSR—fast interrupt processing is initiated. The
following additional steps are performed:
9-6
1. The frozen program counter (return address) is copied to the fast interrupt return address
2. The status register (with the exception of the P4–P0 bits) and the NL bit in the operating
3. The stack pointer (SP) is aligned for long-word accesses.
register (FIRA).
mode register are copied to the fast interrupt status register (FISR).
Fast Interrupt Processing
Figure 9-2. Control Flow in Normal Interrupt Processing
Program
Main
n1
n2
DSP56800E Core Reference Manual
Return From
Jump Address (LBL)
Interrupt
Explicit
(RTI)
Vector Table
Interrupt
JSR
Subroutine
Interrupt
Routine
Interrupt
RTI
ii2
ii3
ii4
iin
Freescale Semiconductor
PC Resumes
Operatio n