dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 399

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

ASRR.W
Operation:
S1 >> S2 → D
D >> S →
Description: This instruction can have two or three operands. Arithmetically shift either the source operand S1 or
Example 1:
Explanation of Example:
Example 2:
Explanation of Example:
Freescale Semiconductor
Before Execution
Before Execution
A2
A2
0
0
D
D to the right by the value contained in the lowest 4 bits of either S2 or S, respectively (or by an im-
mediate integer), and store the result in the destination (D). The shift count can be a 4-bit positive in-
teger, a value in a 16-bit register, or the MSP of an accumulator. For 36- and 32-bit destinations, only
the MSP is shifted and the LSP is cleared, with sign extension from bit 31 (the FF2 portion is ignored).
The result is not affected by the state of the saturation bit (SA).
Prior to execution, the Y1 register contains the value that is to be shifted ($AAAA), and the Y0 register
contains the number by which to shift (least 4 bits of $FFF1 = 1). The contents of the destination reg-
ister are not important prior to execution because they have no effect on the calculated value. The
ASRR.W instruction arithmetically shifts the value $AAAA by 1 bit to the right and places the result
in the destination register A with sign extension (the LSP is cleared).
Prior to execution, A1 contains the value that is to be shifted ($AAAA), and the Y1 register contains
the amount by which to shift ($1). The ASRR.W instruction arithmetically shifts the sign extended val-
ue $AAAA by 1 bit to the right and places the result in the destination register A (the LSP is cleared).
AAAA
AAAA
(no parallel move)
(no parallel move)
1234
0001
A1
Y1
A1
Y1
ASRR.W
ASRR.W
Multi-Bit Arithmetic Right Shift Word
SR
SR
Y1,Y0,A
Y1,A
FFF1
5678
0300
4567
000F
0300
A0
Y0
A0
Y0
Instruction Set Details
; arithmetic right shift of 16-bit A1 by
; least 4 bits of Y1
Assembler Syntax:
ASRR.W
ASRR.W
; arithmetic right shift of 16-bit Y1 by
; least 4 bits of Y0
After Execution
After Execution
A2
A2
F
F
S1,S2,D
S,D
AAAA
D555
D555
0001
A1
Y1
A1
Y1
SR
SR
(no parallel move)
(no parallel move)
ASRR.W
FFF1
0000
0308
0000
000F
0308
A0
Y0
A0
Y0
A-55