dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 241

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

8.1.2
The program counter (PC) is a 21-bit register that contains the address of the next item that is to be fetched
from program memory. The PC can point to instructions, data operands, or addresses of operands. Under
normal operation, all references to this register are implicit; no instruction can manipulate it directly.
The program counter value is split between two locations in the core. The lowest 16 bits are stored in the
PC register, while the top 5 bits are located in the upper word of the status register (SR). See
Section 8.2.2.10, “Program Counter Extension (P0–P4)—Bits 10–14,” for more information.
8.1.3
The looping control unit controls the hardware-accelerated looping capability in the DSP56800E core.
With the REP, DO, and DOSLC instructions, program loops can be executed with very little overhead,
resulting in substantial time savings. For more information on the hardware looping capabilities that are
included in the DSP56800E, see Section 8.5, “Hardware Looping.”
8.1.4
The hardware stack is a 2-deep, 24-bit-wide, last-in-first-out (LIFO) stack that is used to enable the nesting
of hardware loops. It stores the address of the first instruction in a loop, so execution of an outer hardware
loop can continue when an inner hardware loop has completed.
When the stack limit is exceeded, the oldest loop information (top-of-loop address and LF bit) is lost, and a
non-maskable hardware stack overflow interrupt occurs. There is no interrupt on hardware stack
underflow.
The hardware stack can be manipulated under program control using the hardware stack register (HWS),
which is discussed in Section 8.2.7, “Hardware Stack Register.”
8.1.5
The interrupt control unit coordinates interrupt and exception processing in the DSP56800E core. It is
assisted in this task by the interrupt arbitration unit (located outside the core), which performs interrupt
arbitration and indicates when an enabled interrupt request is pending. See Section 8.1.6, “Interrupt
Arbitration Unit.” Interrupt arbitration and the exception processing state are discussed in Section 9.3,
“Exception Processing State,” on page 9-2.
8.1.6
The interrupt arbitration unit is responsible for arbitrating all interrupt requests from the DSP56800E core
and on-chip resources. It typically arbitrates among all available interrupt requests, and then it checks the
priority of the highest request against the interrupt mask bits for the DSC core (I1 and I0 in the SR). If the
requesting interrupt has higher priority than the current priority level of the DSC core, then the unit
generates a single enabled interrupt request signal to the interrupt control unit within the DSP56800E core.
Freescale Semiconductor
Program Counter
Looping Control Unit
Hardware Stack
Interrupt Control Unit
Interrupt Arbitration Unit
The interrupt arbitration unit is not part of the DSP56800E core, but it is
included on any chip that is based on the DSP56800E.
Program Controller
NOTE:
Program Controller Architecture
8-3