dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 285

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

Data ALU instructions such as ADD, CMP, TST, and NEG are typically executed by the data ALU using
Normal Execution. When a multiplication or multi-bit shifting instruction is encountered, it is processed
using Two-Stage Execution (still executing in a single cycle), and it places the data ALU into the Late
Execution state. The data ALU then remains in the Late state until a non–data ALU instruction is executed.
The transitions between states are determined as follows:
The complete list of two-stage instructions follows. Each of these instructions uses two pipeline stages and
places the data ALU into the Late Execution state.
There are three conditions where the data ALU can cause pipeline dependencies. They occur when:
When a data ALU dependency occurs, interlocking hardware on the core automatically stalls the core for
1 cycle to remove the dependency.
Example 10-2 on page 10-6 contains a code sequence demonstrating the behavior of the pipeline with a
variety of different instructions. Note how instructions that are executed using Normal Execution, such as
n2, n3, and n4, complete before the final stage of the pipeline.
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Instructions that are not executed in the data ALU, and multi-cycle data ALU instructions—except
ASLL.L, ASRR.L, and LSRR.L—place the data ALU into the Normal state.
Two-stage instructions and the ASLL.L, ASRR.L, and LSRR.L instructions place the data ALU
into the Late state.
All other instructions keep the data ALU in its current state.
IMAC.L, IMPY.L, IMPY.W
IMACUS, IMACUU, IMPYSU, IMPYUU
MAC, MACR, MPY, MPYR
MACSU, MPYSU
ASLL.W, ASRR.W, LSRR.W
ASLL.L, ASRR.L, LSRR.L
ASRAC, LSRAC
The result of a data ALU instruction that is executed in the Late state is used in the immediately
following instruction as the source register in a move instruction.
The result of a data ALU instruction that is executed in the Late state is used in the immediately
following two-stage instruction as the source register to a multiplication or multi-bit shifting
operation. A dependency does not occur if the result is used in an accumulation, arithmetic, or logic
operation on the immediately following instruction.
An instruction requiring condition codes, such as Bcc, is executed immediately after a data ALU
instruction is executed in the Late state.
Instruction Pipeline
Normal Pipeline Operation
10-5